In: Electrical Engineering
verilog module code
module huffman_decoder(
input clk,
input reset,
input start,
input [2:0] in,
output reg [3:0] out
);
// SIGNAL DECLARATIONS
localparam s0 = 3'd0;
localparam s1 = 3'd1;
localparam s2 = 3'd2;
localparam s3 = 3'd3;
localparam s4 = 3'd4;
localparam s5 = 3'd5;
localparam s6 = 3'd6;
localparam s7 = 3'd7;
reg [2:0] buffer;
// FSM SIGNALS
reg [2:0] ps, ns;
// PRESENT STATE LOGIC
always@(posedge clk, posedge reset)
begin
if(reset)
begin
ps <= s0;
end
else
begin
ps <= ns;
end
end
// NEXT STATE LOGIC
always@*
begin
ns = ps;
case(ps)
s0 : begin
if(start)
begin
buffer = in;
ns = s1;
end
else
begin
ns = s0;
end
end
s1 : begin
if(buffer[2] == 1'b0)
ns = s2;
else if(buffer[1] == 1'b1)
ns = s3;
else
ns = s0;
end
s2 : begin
if(buffer[1] == 1'b0)
ns = s4;
else if(buffer[1] == 1'b1)
ns = s5;
else
ns = s0;
end
s3 : begin
if(buffer[1] == 1'b0)
ns = s6;
else if(buffer[1] == 1'b1)
ns = s7;
else
ns = s0;
end
s4 : begin
if(buffer[0] == 1'b0)
begin
out = 4'b1010;
ns = s0;
end
else if(buffer[0] == 1'b1)
begin
out = 4'b1011;
ns = s0;
end
else
begin
ns = s0;
end
end
s5 : begin
if(buffer[0] == 1'b0)
begin
out = 4'b1100;
ns = s0;
end
else if(buffer[1] == 1'b1)
begin
out = 4'b1101;
ns = s0;
end
else
begin
ns = s0;
end
end
s6 : begin
if(buffer[0] == 1'b0)
begin
out = 4'b1110;
ns = s0;
end
else if(buffer[1] == 1'b1)
begin
out = 4'b1111;
ns = s0;
end
else
begin
ns = s0;
end
end
s7 : begin
if(buffer[0] == 1'b0)
begin
out = 4'b1000;
ns = s0;
end
end
default : begin
ns = s0;
end
endcase
end
endmodule
-------------------
verilog module test bench
module huffman_decoder_tb;
// Inputs
reg clk;
reg reset;
reg start;
reg [2:0] in;
// Outputs
//wire ready;
//wire done_tick;
wire [3:0] out;
// Instantiate the Unit Under Test (UUT)
huffman_decoder uut (
.clk(clk),
.reset(reset),
.start(start),
.in(in),
//.ready(ready),
//.done_tick(done_tick),
.out(out)
);
initial begin
// Initialize Inputs
clk = 0;
reset = 0;
start = 0;
in = 0;
// Wait 100 ns for global reset to finish
#100;
// Add stimulus here
end
always #100 clk = ~clk;
initial begin
#1000 reset = 1'b1;
#1000 reset = 1'b0;
#1000 start = 1'b1;
#1000 in = 3'b000;
#1000 in = 3'b001;
#1000 in = 3'b010;
#1000 in = 3'b011;
#1000 in = 3'b100;
#1000 in = 3'b101;
#1000 in = 3'b110;
end
endmodule
Example Considered in Code
Character Huffman Code Decoded Output
A 000 1010
B 001 1011
C 010 1100
D 011 1101
E 100 1110
F 101 1111
0 110 1000