Question

(Write/Design) both the RTL and Testbench using the Verilog HDL language of the five input majority using the structure modeling approach.

NOTE: Design means RTL code and Testbench covering all possible corner cases

Answer 1

VHDL INTRODUCTION

The basics of the VHDL language for logic design. It describes the use of VHDL as a design entry method for logic design in FPGAs and ASICs. To provide context, it shows where VHDL is used in the FPGA design flow. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. VHDL rules and syntax are explained, along with statements, identifiers and keywords. Finally, use of simulation as a means of testing VHDL circuit designs is demonstrated using ModelSim, a simulator software tool. Programming assignments are used to develop skills and reinforce the concepts presented.

VHDL Logic Design Techniques

In this module use of the VHDL language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique using the programming assignments.

Basics of Verilog

This module introduces the basics of the Verilog language for logic design. It describes the use of Verilog as a design entry method for logic design in FPGAs and ASICs, including the history of Verilog's development. Then a simple example, a 4-bit comparator, is used as a first phrase in the language. Verilog rules and syntax are explained, along with statements, operators and keywords. Finally, use of simulation as a means of testing Verilog circuit designs is demonstrated using ModelSim, a simulator tool. Programming assignments are used to develop skills and reinforce the concepts presented.

Verilog and System Verilog Design Techniques

In this module use of the Verilog language to perform logic design is explored further. Many examples of combinatorial and synchronous logic circuits are presented and explained, including flip-flops, counters, registers, memories, tri-state buffers and finite state machines. Methods of hierarchical design and modular design techniques are explained and demonstrated. How to create test benches is described as a means for design verification. Students are giving ample opportunity to practice and refined their design technique by writing code as required by the programming assignments.

Writing a testbench is as complex as writing the RTL code itself. These days ASICs are getting more and more complex and thus verifying these complex ASIC has become a challenge. Typically 60-70% of time needed for any ASIC is spent on verification/validation/testing. Even though the above facts are well known to most ASIC engineers, still engineers think that there is no glory in verification.

CODE FOR COUNTER

 //-----------------------------------------------------  2 // Design Name : counter  3 // File Name : counter.v  4 // Function : 4 bit up counter  5 // Coder : Deepak  6 //-----------------------------------------------------  7 module counter (clk, reset, enable, count);  8 input clk, reset, enable;  9 output [3:0] count;  10 reg [3:0] count;  11  12 always @ (posedge clk)  13 if (reset == 1'b1) begin  14 count <= 0;  15 end else if ( enable == 1'b1) begin  16 count <= count + 1;  17 end  18  19 endmodule 

 //-----------------------------------------------------  2 // Design Name : counter  3 // File Name : counter.v  4 // Function : 4 bit up counter  5 // Coder : Deepak  6 //-----------------------------------------------------  7 module counter (clk, reset, enable, count);  8 input clk, reset, enable;  9 output [3:0] count;  10 reg [3:0] count;  11  12 always @ (posedge clk)  13 if (reset == 1'b1) begin  14 count <= 0;  15 end else if ( enable == 1'b1) begin  16 count <= count + 1;  17 end  18  19 endmodule 

TEST PLAN

We will write a self-checking test bench, but we will do this in steps to help you understand the concept of writing automated test benches. Our testbench environment will look something like the figure below.

TEST CASES

• Reset Test : We can start with reset de-asserted, followed by asserting reset for few clock ticks and deasserting the reset, See if counter sets its output to zero.
• Enable Test : Assert/deassert enable after reset is applied.
• Random Assert/deassert of enable and reset.

: Design means RTL code and Testbench covering all possible corner cases)

                               always@(state)

                               begin

                                        case(state)

                                      2’b00: B = 5;

                                         2’b01: B = 3;

                                      2’b10: B = 0;

                                        endcase

                               end