Question

Code a 2:4 decoder with registered out. Also write a testbench of the decoder.

Answer 1

Verilog Code

module decoder2to4(A,B,En,Y0,Y1,Y2,Y3);

      input A,B;

      input En;

      output reg Y0,Y1,Y2,Y3;

      always@(A or B or En)

         begin

           if (En)

              case( {A,B} )

                    2'b00: {Y3,Y2,Y1,Y0} = 4'b0001;

                    2'b01: {Y3,Y2,Y1,Y0} = 4'b0010;

                    2'b10: {Y3,Y2,Y1,Y0} = 4'b0100;

                    2'b11: {Y3,Y2,Y1,Y0} = 4'b1000;

                    default: {Y3,Y2,Y1,Y0} = 4'b0000;

             endcase

          if (En==0)

                   {Y3,Y2,Y1,Y0} = 4'b0000;

       end

endmodule

Test Bench

module testdecoder;

      wire Y0,Y1,Y2,Y3;

      reg A,B;

      reg En;

      decoder2to4   UUT(A,B,En,Y0,Y1,Y2,Y3);    // Unit under test

      initial

         begin

             A= 1'b0;

             B= 1'b0;

             En=1'b0;

             #9;

            En = 1'b1;

            #10;

             A= 1'b0;

             B= 1'b1;

             #10;

             A= 1'b1;

             B= 1'b0;

             #10;   

             A= 1'b1;

             B= 1'b1;

            #5;

            En = 1'b0;

            #5;

         $stop

   end

endmodule