In: Electrical Engineering
write a verilog code to implement a digital system that has an odd counter that counts from 1 to 11. Also, this system has an output Y that detects a specific number in the odd counter. Test your code when you detect the number 3, the output Y is 1, if the counter value is set to 3, otherwise 0.
Solution:
Verilog code is developed to get the counter to count only odd numbers from 1,3,5,7,9 and 11 and reset to 1. It has one output called Y = 1 when the count is equal to 3.
Verilog code:
//////////////////////////////////////////////////////////////////////////////////
module count4bit (Clock, reset, Y, Q);
input Clock, reset;
output Y;
output reg [3:0] Q;
always @(posedge Clock)
if (reset)
Q <= 1;
else
begin
Q <= Q+2;
if(Q > 10)
Q<= 1;
end
assign Y= (Q == 3);
endmodule
///end of the code/////////////////
Test bench code:
module tb_Odd;
// Inputs
reg Clock;
reg reset;
// Outputs
wire Y;
wire [3:0] Q;
// Instantiate the Unit Under Test (UUT)
count4bit uut (
.Clock(Clock),
.reset(reset),
.Y(Y),
.Q(Q)
);
initial begin
// Initialize Inputs
Clock = 0;
reset = 1;
// Wait 100 ns for global reset
to finish
#100;
reset = 0;
// Add stimulus here
end
initial
forever #5 Clock = ~ Clock;
endmodule
//end of the test bench code/////////////////
SImulated results:
The design has inputs Clock and reset
outputs Y and Q