Question

Write a verilog code for digital clock and display it’s seven segment using fpga?

Answer 1

verilog code :

library IEEE

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.numeric_std.all;

entity digital_clock is

port(

clk: in std_logic;

rst_n: in std_logic;

H_in1: in std_logic_vector(1 downto 0);

H_in0: in std_logic_vector(3 downto 0);

M_in1: in std_logic_vector(3 downto 0);

M_in0: in std_logic_vector(3 downto 0);

H_out1: out std_logic_vector(6 downto 0);

H_out0: out std_logic_vector(6 downto 0);

M_out1: out std_logic_vector(6 downto 0);

M_out0: out std_logic_vector(6 downto0);

end digital_clock;

architecture Behavioural of digital_clock is

component bin2hex

port (

Bin : in std_logic_vector(3 downto o);

Hout out std_logic_vector(6 downto 0);

end component;

component clk_div

port(

clk_50: in std_logic;

clk_ls: out std_logic );

end component ;

signal clk_is : std_logic ;

signal H_out1_bin :std_logic_vector(3 downto 0);

signal H_out0_bin: std_logic_vector(3 downto 0);

signal M_out1_bin: std_logic_vector(3 downto 0);

signal M_out0_bin: std_logic_vector(3 downto 0);

begin

create_ls_clock:clk_div port map(clk_50 =>clk, clk_ls =>clk_ls);

process(clk_ls,rst_n) begin

if(rst_n ='0') then

counter_hour <=to_integer (unsigned(H_in1))*10+ to_integer(unsigned(H_in0));

counter_minute <=to_integer(unsigned(M_in1))*10+to_integer(unsigned(M_in0));

counter_second<=0;

elseif(rising_edge(clk_ls)) then counter_second<=counter_second+1;

if(counter_second>=59) then

counter_minute <=0;

counter_hour<=counter_hour+1;

if(counter_hour <=24) then

if(counter_hour>=24) then

counter_hour <=0;

end if;

end if;

emd if;

end if;

end process;