verilog code of a 64 x64 array with 128 parameters please include test bench

verilog code of a 64 x64 array with 128 parameters

please include test bench

Expert Solution


module array_multiplier_tb;

reg [31:0] a, b;
wire [31:0] y;

array_multiplier #(
        .width(32)
) uut (
        .a(a),
        .b(b),
        .y(y)
); 

reg [31:0] xrnd = 1;
task xorshift32;
begin
        xrnd = xrnd ^ (xrnd << 13);
        xrnd = xrnd ^ (xrnd >> 17);
        xrnd = xrnd ^ (xrnd <<  5);
end endtask

integer i;
initial begin
        // $dumpfile("array_multiplier_tb.vcd");
        // $dumpvars(0, array_multiplier_tb);

        for (i = 0; i < 100; i = i+1)
        begin
                #10;

                xorshift32;
                a <= xrnd;
                xorshift32;
                b <= xrnd;

                #10;

                $display("%d * %d = %d (%d)", a, b, y, a*b);
                if (y != a*b) begin
                        $display("ERROR!");
                        $finish;
                end
        end
        $display("PASSED.");
end

endmodule

The above is your test branch

module array_multiplier_pipeline(clk, a, b, y);

parameter width = 8;

input clk;
input [width-1:0] a, b;
output [width-1:0] y;

reg [width-1:0] a_pipeline [0:width-2];
reg [width-1:0] b_pipeline [0:width-2];
reg [width-1:0] partials [0:width-1];
integer i;

always @(posedge clk) begin
    a_pipeline[0] <= a;
    b_pipeline[0] <= b;
    for (i = 1; i < width-1; i = i+1) begin
        a_pipeline[i] <= a_pipeline[i-1];
        b_pipeline[i] <= b_pipeline[i-1];
    end

    partials[0] <= a[0] ? b : 0;
    for (i = 1; i < width; i = i+1)
        partials[i] <= (a_pipeline[i-1][i] ? b_pipeline[i-1] << i : 0) +
                partials[i-1];
end

assign y = partials[width-1];

endmodule

venereology answered 3 years ago

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