Question

First, draw the state machine for the following program. Then write the corresponding Verilog behavioral code.

Input: X - 1 bit number

Output: Z - 1 bit number

Clock: clk (State will change at positive edge of the clock)

Output will be equal to one if X_n-2 X_n-1 X_n = 011 or X_n-2 X_n-1 X_n = 101

Answer 1

Please please give me a thumbs up sir:

•Code for detecting 011 and 101 :

// Code your design here

module det( input clk,

input rstn,

input X,

output Z );

parameter S0 = 0,

S1 = 1,

S2 = 2,

S3 = 3,

S4 = 4; // defining states as parameters

reg [2:0] cur_state, next_state; //defining states as registers

reg Z;

always @ (posedge clk) begin

if (!rstn) begin

cur_state <= S0;

assign Z=0;

end

else

begin

cur_state <= next_state;

assign Z=0;

end

end

always @ (cur_state or X) begin

case (cur_state) // assigning next states and output

S0: begin

if (X) begin next_state <= S3;

assign Z=0;

end

else begin next_state <= S1;

assign Z=0;

end

end

S1: begin

if (X) begin next_state <= S2;

assign Z=0;

end

else begin next_state <= S1;

assign Z=0;

end

  

end

S2 : begin

if (X) begin next_state <= S3;

assign Z=1;

end

else begin next_state <= S0;

assign Z = 0;

end

  

end

S3: begin

if (X) begin next_state <= S2;

assign Z=0;

end

else begin next_state <= S4;

assign Z=0;

end

end

S4: begin

if (X) begin next_state <= S3;

assign Z = 1;

end

else begin next_state <= S0;

assign Z =0;

end

  

end

endcase

end

endmodule

•Testbench;

// Code your testbench here

// Code your testbench here

module tb;

reg clk,X,rstn;

wire Z;

det dut(.clk(clk),

.rstn(rstn),

.X(X),

.Z(Z));

initial

clk=1'b0;

always

#20clk=~clk;

initial

begin

X=0;

rstn=1;

  

#20

X=0;

rstn=0;

  

#20

X=1;

rstn=0;

  

#20

X=1;

rstn=0;

  

#20

X=0;

rstn=0;

  

#20

X=0;

rstn=0;

#20

X=1;

  

#20

X=0;

  

#20

X=1;

#20

X=0;

#20

X=0;

#20

X=1;

#20

X=1;

#20

X=0;

#20

X=0;

#20

X=0;

#20

X=0;

end

initial

  

#1300 $finish;

  

initial

  

begin

  

$dumpfile("dump.vcd");

  

$dumpvars;

  

end

endmodule