Question

Create a counter that continuously counts odd numbers backwards (i.e from ‘F’ to ‘0’) and display it on 7-sd by using the Verilog code.

On this part, you are required to use the clock from the FPGA board. However, the clock frequency is 100 MHz, and it is too fast to be used (10 ?s). Thus, we need to derive a slower clock with a speed of almost 1 s, which the frequency of it is 1 Hz. This process is called clock division.

MY FPGA is BASYS 3 and program must be written in verilog. Could you please help me? At least write the design code.

If you help me, I will be the happiest person in the world.

Answer 1

use structural modelling.

Clock divider and counter module is given below.

Instantiate these modules in a top.v file (create ur own).

module clock_divider (clk_100MHZ, clk_1HZ);

input clk_100MHZ;

output clk_1HZ;

reg [26 : 0] counter = 27'd0;

reg clkout = 1'b0;

always @(posedge clk_100MHZ)

begin

if (counter == 27'd50000000) // count 50x10e6 and toggle to get 1 HZ

begin

counter <= 27'd0;

clkout <= ~clkout;

end

else

counter <= counter + 1;

end

assign clk_1HZ = clkout;

endmodule

module odd_counter (clk_1HZ, reset, display, binary);

input clk_1HZ, reset;

output reg [6:0] display;

output [3:0] binary;

parameter fifteen = 4'b1111, thirteen = 4'b1101, eleven = 4'b1011, nine = 4'b1001, seven = 4'b0111, five = 4'b0101, three = 4'b0011, one = 4'b0001;

reg [3:0] state = 4'b1111;

reg [3:0] next_state;

always @ (posedge clk_1HZ)

begin

if (reset == 1'b1)

state <= fifteen;

else

state <= next_state;

end

always @ (state)

begin

case (state)

fifteen: begin next_state <= thirteen;

display <= 7'b1000111;

end

thirteen: begin next_state <= eleven;

display <= 7'b0111101;

end

eleven: begin next_state <= nine;

display <= 7'b0011111;

end

nine: begin next_state <= seven;

display <= 7'b1111011;

end

seven: begin next_state <= five;

display <= 7'b1110000;

end

five: begin next_state <= three;

display <= 7'b1011011;

end

three: begin next_state <= one;

display <= 7'b1111000;

end

one: begin next_state <= fifteen;

display <= 7'b0110000;

end

default : next_state <= fifteen;

endcase

end

assign binary = state;

endmodule