Question

Digital System Design

1. Write the verilog HDL code for 2-4 decoder (Gate level modeling) along with the testbench and simulate using ModelSim.

   
   Upload the assignment (i) code (ii) testbench (iii) simulation in single pdf file.

Answer 1

code:

raw_code :

`timescale 1ns / 1ps
module decoder(a,b,e,D);

input a,b,e; //declaring inputs
output [3:0] D; //declaring output

//gate level implementation of decoder
and a1(D[0],~a,~b,e);
and a2(D[1],~a,b,e);
and a3(D[2],a,~b,e);
and a4(D[3],a,b,e);

endmodule

test_bench:

raw_code :

module test_decoder();
reg a,b,e; //declaring inputs as register
wire [3:0]D;

decoder d(a,b,e,D); //instantiation

initial begin
//Initialize inputs
e = 1;
a = 1'b0; #20;
b = 1'b0; #20;
b = 1'b1; #20;
a = 1'b1; #20;
  
end
endmodule

output :

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