Question

1.Write verilog code for a 8:1 Mux using the blocks of 2:1 Mux; Draw the block diagram for this design and write the truth table to prove that the design works as intended.

2. Write verilog code for a 16:1 Mux using the blocks of 4:1 Mux; Draw the block diagram for this design and write the truth table to prove that the design works as intended.

Answer 1

module Mux8by1_by_using_2by1(i7,i6,i5,i4,i3,i2,i1,i0,s2,s1,s0,out);

input i7,i6,i5,i4,i3,i2,i1,i0,s2,s1,s0; //Input ports declaration
output out;                              //Output ports declaration              
wire w1,w2,w3,w4,w5,w6;                  //Wires(internal Connections) declaration

    mux21 m1(i1,i0,s0,w1);         // 2to1 Multiplexer instantiations
    mux21 m2(i3,i2,s0,w2);
    mux21 m3(i5,i4,s0,w3);
    mux21 m4(i7,i6,s0,w4);
    mux21 m5(w2,w1,s1,w5);
    mux21 m6(w4,w3,s1,w6);
    mux21 m7(w6,w5,s2,out);

endmodule                         

// Code for Instantiated Module
module mux21(I1,I0,S,F);      
    input I1,I0,S;       //Input ports declaration
    output F;            //Output ports declaration

    assign F = S?I1:I0; //Assigning expression for output

endmodule

//Top level Module
module Mux_16by1_using_4by1(i15,i14,i13,i12,i11,i10,i9,i8,i7,i6,i5,i4,i3,i2,i1,i0,s3,s2,s1,s0,out);
    input i15,i14,i13,i12,i11,i10,i8,i9,i7,i6,i5,i4,i3,i2,i1,i0,s3,s2,s1,s0;    //Input ports declaration
    output out;                                     //Output Ports declaration
    wire w1,w2,w3,w4;                               //Wires(internal Connections) declaration
  
    four_by_one_mux m1(i0,i1,i2,i3,s0,s1,w1);       // 4to1 Multiplexer instantiations
    four_by_one_mux m2(i4,i5,i6,i7,s0,s1,w2);
    four_by_one_mux m3(i8,i9,i10,i11,s0,s1,w3);
    four_by_one_mux m4(i12,i13,i14,i15,s0,s1,w4);
    four_by_one_mux m5(w1,w2,w3,w4,s2,s3,out);
  
endmodule

//Code for instantiated Module
module four_by_one_mux(k0,k1,k2,k3,se0,se1,out1);
    input k0,k1,k2,k3,se0,se1;      //Input ports declaration
    output out1;                    //OUtput ports declaration
    wire w1,w2,w3,w4,n1,n2;         //Wires(internal connections) declaration
  
    not a(n1,se0);              //Functional description of 4to1 Multiplexer
    not b(n2,se1);
    and a1(w1,k0,n1,n2);
    and a2(w2,k1,se0,n2);
    and a3(w3,k2,n1,se1);
    and a4(w4,k3,se0,se1);
    or a5(out1,w1,w2,w3,w4);
  
endmodule