Question

I am trying to create an 8-bit random number generator in verilog code using a mux, a d flip flop and a LFSR not sure what I am doing wrong but need some help with getting it working properly any help would be greatly appreciated.

here is what I have so far:

module RNG #(parameter size=8)(output [7:0]SO,output [7:0] RN,input clk,rst,input[size-1:0]seed,input L);
   wire [7:0] Sin=SO[7]^SO[5]^SO[4]^SO[3];
   ffw F1 (SO,clk,rst,Sin);
   MUX M1 (Sin,seed,{SO[size-2:0],next},L);
   xor X1 (next,SO[6],SO[7]);
   assign RN=next;
endmodule
module ffw #(parameter size=8)(output reg [size-1:0]SO,input clk,rst,input [size-1:0] Sin);
   always @(posedge clk or posedge rst)
       begin
       if(rst==1)
           SO=0;
       else
           SO=Sin;
       end
endmodule
// input A1 = Seed, input B0 =Sin ,L=SEL,
module MUX #(parameter size=8)(output[size-1:0]SO,input[size-1:0]Sin,seed,input L);
   assign SO = (L) ? Sin:seed;
endmodule
module RNG_TB();
   reg clk;
   reg rst,L;
   wire [7:0] SO;
   reg [7:0] seed;
   wire [7:0] RN;
   integer x;
   RNG RN1 (SO,RN,clk,rst,seed,L);
   initial begin
       x=0; clk=0; rst=1; L=0; #5;
       rst=0; L=0; seed=255; #5;
       rst=0; L=1; seed=255; clk=1; #5
       L=0;
       repeat (10) begin
           clk = ~clk; #10;
           x=x+1;
           $display("x=%d,clk=%d,SO=%b",x,clk,SO);
           clk = ~clk; #10;
       end
   end
endmodule

Answer 1

//You are assigning Sin at two places.

//Sin=SO[7]^SO[5]^SO[4]^SO[3];

// And at mux instance. I removed one. If you need some other Design let me know. Now it's working. And at mux I changed look at mux assign statement.

module RNG #(parameter size=8)(output [7:0]SO,output [size-1:0]RN,input clk,rst,input[size-1:0]seed,input L);
wire [7:0] Sin;//=SO[7]^SO[5]^SO[4]^SO[3];
ffw F1 (SO,clk,rst,Sin);
MUX M1 (Sin,{SO[size-2:0],next},seed,L);
xor X1 (next,SO[6],SO[7]);
assign RN=next;
endmodule
module ffw #(parameter size=8)(output reg [size-1:0]SO,input clk,rst,input [size-1:0] Sin);
always @(posedge clk or posedge rst)
begin
if(rst==1)
SO <= 0;
else
SO <= Sin;
end
endmodule
// input A1 = Seed, input B0 =Sin ,L=SEL,
module MUX #(parameter size=8)(output[size-1:0]SO,input[size-1:0]Sin,seed,input L);
assign SO = (L) ? seed:Sin; // changed here to get output correct
endmodule

module RNG_TB();
reg clk;
reg rst,L;
wire [7:0] SO;
reg [7:0] seed;
wire [7:0] RN;
integer x;
RNG RN1 (SO,RN,clk,rst,seed,L);
initial begin
$dumpfile("dump.vcd"); $dumpvars;
x=0; clk=0; rst=1; L=0; #5;
rst=0; L=0; seed=255; #5;
rst=0; L=1; seed=255; clk=1; #5
L=0;
repeat (10) begin
clk = ~clk; #10;
x=x+1;
$display("x=%d,clk=%d,SO=%b",x,clk,SO);
clk = ~clk; #10;
end
end
endmodule