Question

Question 1: A Multiplexer (MUX)

a) Write truth table and draw symbol for a 4-to-1 MUX. (1 mark)

b) Write VHDL code for the above multiplexer. (1 mark)

c) Write VHDL code for a test bench and simulate the design. (1 mark)

d) Implement the design on FPGA, with inputs connected to switches and output to LED. (1 mark)

Answer 1

Truth Table:

Input Pin = A B C D

Output Pin = O

Select Pin = S0 S1

S0 S1 O

0 0 A

0 1 B

1 0 C

1 1 D

VHDL CODE:

library IEEE;

use IEEE.STD_LOGIC_1164.all;

entity mux_4to1 is

port(

     A,B,C,D : in STD_LOGIC;

     S0,S1: in STD_LOGIC;

     O: out STD_LOGIC

  );

end mux_4to1;

architecture bhv of mux_4to1 is

begin

process (A,B,C,D,S0,S1) is

begin

  if (S0 ='0' and S1 = '0') then

      O <= A;

  elsif (S0 ='0' and S1 = '1') then

      O <= B;

  elsif (S0 ='1' and S1 = '0') then

      O <= C;

  else

      O <= D;

  end if;

end process;

end bhv;

VHDL Testbench:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY tb_mux IS

END tb_mux;

ARCHITECTURE behavior OF tb_mux IS

    -- Component Declaration for the Unit Under Test (UUT)

    COMPONENT mux_4to1

    PORT(

         A : IN std_logic;

         B : IN std_logic;

         C : IN std_logic;

         D : IN std_logic;

         S0 : IN std_logic;

         S1 : IN std_logic;

         O : OUT std_logic

        );

    END COMPONENT;

   --Inputs

   signal A : std_logic := '0';

   signal B : std_logic := '0';

   signal C : std_logic := '0';

   signal D : std_logic := '0';

   signal S0 : std_logic := '0';

   signal S1 : std_logic := '0';

    --Outputs

   signal O : std_logic;

BEGIN

    -- Instantiate the Unit Under Test (UUT)

   uut: mux_4to1 PORT MAP (

          A => A,

          B => B,

          C => C,

          D => D,

          S0 => S0,

          S1 => S1,

          O => O

        );

   -- Stimulus process

   stim_proc: process

   begin

      -- hold reset state for 100 ns.

      wait for 100 ns;

    A <= '1';

    B <= '0';

    C <= '1';

    D <= '0';       

    S0 <= '0'; S1 <= '0';

      wait for 100 ns;

    S0 <= '1'; S1 <= '0';

      wait for 100 ns;

    S0 <= '0'; S1 <= '1';

        wait for 100 ns;   

    S0 <= '0'; S1 <= '1';  

        wait for 100 ns;   

    end process;

END;

The above code is trivial and I have taken it from allaboutfpga.

The code is self-explanatory and is in confirmation with the truth table I have drawn in the beginning.

PLEASE LEAVE A THUMBS UP