Question

In: Electrical Engineering

Using the following VHDL code for an 8 bit adder, make the sum be displayed on...

Using the following VHDL code for an 8 bit adder, make the sum be displayed on the seven segment display of an Elbert V2 Spartan 3A FPGA Board.

VHDL:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity state_bit_adder is

Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
           D : in STD_LOGIC;
           Enable : out STD_LOGIC_vector (2 downto 0);
           input: in std_logic_vector(7 downto 0);
           SUM: out std_logic_vector(8 downto 0));

end state_bit_adder;

architecture Behavioral of state_bit_adder is
type statetype is (start, secondstate);
signal state, nextstate: statetype;

signal tempsum1, tempsum: STD_LOGIC_VECTOR (8 downto 0);

begin
Enable <= "110";
process(clk, reset)
begin
if(reset ='0') then
state <= start;
elsif rising_edge(clk) then
state <= nextstate;
end if;
end process;

process(state, input, D)
begin
case (state) is
when start =>
tempsum1 <= ('0'&input);
if (D = '0') then
nextstate <= secondstate;
end if;

when secondstate =>
tempsum <= ('0'&input);
if (D = '0') then
nextstate <= start;
end if;
end case;
end process;

SUM <= tempsum1 + tempsum;

End Behavioral;

Constraint File:

#####################################################################################################
## DP Switches
#####################################################################################################

Expert Solution

The VHDL code will changed as given below to include the seven segment display. Here, the output SUM is displaye in the seven segment display as hexadecimal.

VHDL Code:

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity state_bit_adder is
Port ( clk : in STD_LOGIC;
reset : in STD_LOGIC;
D : in STD_LOGIC;

input: in std_logic_vector(7 downto 0);
Enable : out STD_LOGIC_vector (2 downto 0);
Seven_Segment_Display : out STD_LOGIC_VECTOR (7 downto 0));
end state_bit_adder;

architecture Behavioral of state_bit_adder is
type statetype is (start, secondstate);
signal state, nextstate: statetype;

signal tempsum1, tempsum,SUM: STD_LOGIC_VECTOR (8 downto 0);

signal bcd0,bcd1,bcd2: STD_LOGIC_VECTOR (3 downto 0);

variable Seven_Segment_Display_output : std_logic_vector (7 downto 0) := (others => '1');

begin
Enable <= "110";
process(clk, reset)
begin
if(reset ='0') then
state <= start;
elsif rising_edge(clk) then
state <= nextstate;
end if;
end process;

process(state, input, D)

begin
case (state) is
when start =>
tempsum1 <= ('0'&input);
if (D = '0') then
nextstate <= secondstate;
end if;

when secondstate =>
tempsum <= ('0'&input);
if (D = '0') then
nextstate <= start;
end if;
end case;
end process;

SUM <= tempsum1 + tempsum;

process(SUM)

begin

--display 1st digit (LSD)

bcd0<=SUM(3 downto 0);

Enable <= "110";

case bcd0 is
when 0 => Seven_Segment_Display_output(7 downto 0) := B"00000010";
when 1 => Seven_Segment_Display_output(7 downto 0) := B"10011110";
when 2 => Seven_Segment_Display_output(7 downto 0) := B"00100100";
when 3 => Seven_Segment_Display_output(7 downto 0) := B"00001100";
when 4 => Seven_Segment_Display_output(7 downto 0) := B"10011000";
when 5 => Seven_Segment_Display_output(7 downto 0) := B"01001000";
when 6 => Seven_Segment_Display_output(7 downto 0) := B"01000000";
when 7 => Seven_Segment_Display_output(7 downto 0) := B"00011110";
when 8 => Seven_Segment_Display_output(7 downto 0) := B"00000000";
when 9 => Seven_Segment_Display_output(7 downto 0) := B"00011000";

when 10 => Seven_Segment_Display_output(7 downto 0) := B"00010000";
when 11 => Seven_Segment_Display_output(7 downto 0) := B"11000000";
when 12 => Seven_Segment_Display_output(7 downto 0) := B"01100010";
when 13 => Seven_Segment_Display_output(7 downto 0) := B"01000010";
when 14 => Seven_Segment_Display_output(7 downto 0) := B"00001100";
when 15 => Seven_Segment_Display_output(7 downto 0) := B"00011100";
when others => Seven_Segment_Display_output(7 downto 0) := B"11111111";
end case;

Seven_Segment_Display(7 downto 0) <= Seven_Segment_Display_output(7 downto 0);

--display 2nd digit

Enable <= "101";

bcd1<=SUM(7 downto 4);

case bcd1 is
when 0 => Seven_Segment_Display_output(7 downto 0) := B"00000010";
when 1 => Seven_Segment_Display_output(7 downto 0) := B"10011110";
when 2 => Seven_Segment_Display_output(7 downto 0) := B"00100100";
when 3 => Seven_Segment_Display_output(7 downto 0) := B"00001100";
when 4 => Seven_Segment_Display_output(7 downto 0) := B"10011000";
when 5 => Seven_Segment_Display_output(7 downto 0) := B"01001000";
when 6 => Seven_Segment_Display_output(7 downto 0) := B"01000000";
when 7 => Seven_Segment_Display_output(7 downto 0) := B"00011110";
when 8 => Seven_Segment_Display_output(7 downto 0) := B"00000000";
when 9 => Seven_Segment_Display_output(7 downto 0) := B"00011000";

when 10 => Seven_Segment_Display_output(7 downto 0) := B"00010000";
when 11 => Seven_Segment_Display_output(7 downto 0) := B"11000000";
when 12 => Seven_Segment_Display_output(7 downto 0) := B"01100010";
when 13 => Seven_Segment_Display_output(7 downto 0) := B"01000010";
when 14 => Seven_Segment_Display_output(7 downto 0) := B"00001100";
when 15 => Seven_Segment_Display_output(7 downto 0) := B"00011100";
when others => Seven_Segment_Display_output(7 downto 0) := B"11111111";
end case;

Seven_Segment_Display(7 downto 0) <= Seven_Segment_Display_output(7 downto 0);

--display 3rd digit (MSD)

Enable <= "011";

bcd2<=SUM(9 downto 8);

case bcd2 is
when 0 => Seven_Segment_Display_output(7 downto 0) := B"00000010";
when 1 => Seven_Segment_Display_output(7 downto 0) := B"10011110";
when 2 => Seven_Segment_Display_output(7 downto 0) := B"00100100";
when 3 => Seven_Segment_Display_output(7 downto 0) := B"00001100";
when 4 => Seven_Segment_Display_output(7 downto 0) := B"10011000";
when 5 => Seven_Segment_Display_output(7 downto 0) := B"01001000";
when 6 => Seven_Segment_Display_output(7 downto 0) := B"01000000";
when 7 => Seven_Segment_Display_output(7 downto 0) := B"00011110";
when 8 => Seven_Segment_Display_output(7 downto 0) := B"00000000";
when 9 => Seven_Segment_Display_output(7 downto 0) := B"00011000";

when 10 => Seven_Segment_Display_output(7 downto 0) := B"00010000";
when 11 => Seven_Segment_Display_output(7 downto 0) := B"11000000";
when 12 => Seven_Segment_Display_output(7 downto 0) := B"01100010";
when 13 => Seven_Segment_Display_output(7 downto 0) := B"01000010";
when 14 => Seven_Segment_Display_output(7 downto 0) := B"00001100";
when 15 => Seven_Segment_Display_output(7 downto 0) := B"00011100";
when others => Seven_Segment_Display_output(7 downto 0) := B"11111111";
end case;

Seven_Segment_Display(7 downto 0) <= Seven_Segment_Display_output(7 downto 0); 

end process;

End Behavioral;

Constraint File:

############Clock 12MHz

NET "clk" LOC=P129 | IOSTANDARD = LVTTL | PERIOD=12MHz;

NET "D" CLOCK_DEDICATED_ROUTE = FALSE;

###########DP Switches

Manojponduru answered 1 year ago

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Using the following VHDL code for an 8 bit adder, make the sum be displayed on...

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