Question

Objective: Design and test a 4-bit Right shift register with serial input.

Part I

Use D flip-flops (FF) in your design (Memory → D Flip-Flop). Ensure the output of each FF (Q) goes to an output so the functionally of the shift register can be verified. All 4 Flip-Flop need to share a common clock which is connected to an input you can control. Verify the functionally of the circuit by changing the input value and toggling the clock. You should see the value in the register shift to the right.

Part II

Modify the circuit so that if the register contains 1010 OR 0111 an output signal goes active (logic 1). Verify the functionally of the circuit by shifting in the two values to be detected and ensure the output goes high (logic 1).

Please use some kind of software and attach screenshots

Answer 1

1. The shift register using D flipflops can be simply built by cascading all d flipflops . That is the first FF output will be input to second FF and second FF output will be input to third FF and so on. The !preset and !clear are set to one for default working mode of DFF. Below figures are the snapshots of circuit for every shift

2. In order to output 1 for 0111 and 1010 we need to minimize the function using Boolean alzebra

0111 =A̅BCD and 1010 =AB̅CD̅

Function = A̅BCD + AB̅CD̅ = C (A̅BD + AB̅D̅).

This is implemented using three and gates and one or gate as shown in picture.

Below are the pictures verifying circuit works as predicted .