Question

make 4 bit universal shift register in vhdl plz include the test bench. I will rate

Answer 1

4 BIT VHDL CODE

library IEEE;  
 use IEEE.STD_LOGIC_1164.ALL;  
 use IEEE.STD_LOGIC_ARITH.ALL;  
 use IEEE.STD_LOGIC_UNSIGNED.ALL;  
 -- ENTITY  
 entity four_bit_shifter is  
   Port ( Data_In : in std_logic_vector(3 downto 0);  
       G : in std_logic_vector(2 downto 0);  
       Output : out std_logic_vector(3 downto 0));  
 end four_bit_shifter;  
 -- ARCHITECTURE  
 architecture Behavioral of four_bit_shifter is  
 -- COMPONENTS  
 component nBitShiftRotateM   
   generic(n:positive:=4);  
       Port (Data_In1 : in std_logic_vector(n-1 downto 0);  
             Data_In2 : in std_logic_vector(n-1 downto 0);  
             Right_In : in std_logic;  
             Right_Select : in std_logic;  
             Left_In : in std_logic;  
             Left_Select : in std_logic;  
             Control : in std_logic_vector (1 downto 0);  
          Output : out std_logic_vector (n-1 downto 0));  
 end component;  
 component shiftcontrollogic   
   Port ( input : in STD_LOGIC_VECTOR (2 downto 0);  
       output : out STD_LOGIC_VECTOR (1 downto 0));  
 end component;  
 -- SIGNAL  
 signal shift_control : std_logic_vector (1 downto 0);  
 begin  
      logic_device : shiftcontrollogic port map (G, shift_control);  
      -- instantiate an n-bit shift_rotate device with generic value "n"   
      -- mapped to a bit-width of 4. Note that the second data input is   
      -- connected directly to ground by using the 4-bit value "0000".   
      shift_device : nBitShiftRotateM  generic map (4) port map (Data_In, "0000", G(0), G(1), G(0), G(1), shift_control, Output);   
 end Behavioral;  

Test bench code:

LIBRARY ieee;  
 USE ieee.std_logic_1164.ALL;  
 USE ieee.std_logic_unsigned.all;  
 USE ieee.numeric_std.ALL;  
 ENTITY four_bit_shifter_tb_vhd IS  
 END four_bit_shifter_tb_vhd;  
 ARCHITECTURE behavior OF four_bit_shifter_tb_vhd IS   
      -- Component Declaration for the Unit Under Test (UUT)  
      COMPONENT four_bit_shifter  
      PORT(  
           Data_In : IN std_logic_vector(3 downto 0);  
           G : IN std_logic_vector(2 downto 0);       
           Output : OUT std_logic_vector(3 downto 0)  
           );  
      END COMPONENT;  
      --Inputs  
      SIGNAL Data_In : std_logic_vector(3 downto 0) := (others=>'0');  
      SIGNAL G : std_logic_vector(2 downto 0) := (others=>'0');  
      --Outputs  
      SIGNAL Output : std_logic_vector(3 downto 0);  
 BEGIN  
      -- Instantiate the Unit Under Test (UUT)  
      uut: four_bit_shifter PORT MAP(  
           Data_In => Data_In,  
           G => G,  
           Output => Output  
      );  
      tb : PROCESS  
      BEGIN  
           -- Wait 100 ns for global reset to finish  
           wait for 100 ns;  
        G <= "000";            -- test Pass  
           Data_In <= "0101";  
           wait for 100 ns;  
        G <= "001";            -- test rotate left  
           Data_In <= "0101";  
           wait for 100 ns;  
        G <= "010";            -- test shift left (insert 0)  
           Data_In <= "1111";  
           wait for 100 ns;  
        G <= "011";            -- test shift left (insert 1)  
           Data_In <= "0000";  
           wait for 100 ns;  
        G <= "100";            -- test Pass  
           Data_In <= "1010";  
           wait for 100 ns;  
        G <= "101";            -- test rotate right  
           Data_In <= "1010";  
           wait for 100 ns;  
        G <= "110";            -- test shift right (insert 0)  
           Data_In <= "1111";  
           wait for 100 ns;  
        G <= "111";            -- test shift right (insert 1)  
           Data_In <= "0000";  
           wait for 100 ns;  
           -- Place stimulus here  
           wait; -- will wait forever  
      END PROCESS;  
 END;