Question

Design and Test an 8-bit Adder using 4-bit adder. Use

4-bit adder coded in class using full adder that is coded using data flow model. Use test bench

to test 8-bit adder and consider at least five different test vectors to test it.

Answer 1

//verilog top level code for 8 bit adder using 4 bit adders as internal module instantiations

module adder_8bit ( A,B,Cin,S,Cout);

  

//input ports declarations

input [7:0] A,B;

input Cin;

  

//output port declarations

output [7:0] S; //sum output

output Cout ; //carry output

//internal signal declarations

wire C ;

  

//instantiation of 4 bit adders

adder_4bit U0 ( A[3:0],B[3:0],Cin,S[3:0],C);

adder_4bit U1 ( A[7:4],B[7:4],C,S[7:4],Cout);

  

endmodule

  

//verilog code for 4 bit adder using full adders as internal module instantiations

module adder_4bit ( A,B,Cin,S,Cout);

  

//input ports declarations

input [3:0] A,B;

input Cin;

  

//output port declarations

output [3:0] S; //sum output

output Cout ; //carry output

  

  

//internal signal declarations

wire [2:0] c ;

  

//instantiaion of full adders

fulladder F0 ( A[0] , B[0] , Cin , S[0] , c[0] );

fulladder F1 ( A[1] , B[1] , c[0] , S[1] , c[1] );

fulladder F2 ( A[2] , B[2] , c[1] , S[2] , c[2] );

fulladder F3 ( A[3] , B[3] , c[2] , S[3] , Cout );

  

endmodule

  

// DATAFLOW verilog code full adder module

module fulladder (

//input ports declarations

input A,B,Cin,

//output port declartions

output S,Cout);

  

//sum logic

assign S = (A ^ B ^ Cin);

//carry logic

assign Cout = ( A & B ) | ( B & Cin) | (A & Cin) ;

  

endmodule

// verilog testbench code for top module of 8 bit adder  

module test_adder_8bit ;

  

//inputs

reg [7:0] A,B;

reg Cin;

  

//outputs

wire [7:0] S;

wire Cout;

  

//instantiate UUT (unit under test) of top module

adder_8bit UUT (.A(A),.B(B),.Cin(Cin),.S(S),.Cout(Cout));

  

//test vectore for 8 bit adder (input stimulus generations)

initial begin

$dumpfile ("waves.vcd");

$dumpvars;

A = 8'b00101101 ; B = 8'b00101101; Cin = 1'b0; #10;

A = 8'b00100101 ; B = 8'b00100001; Cin = 1'b0; #10;

A = 8'b10100001 ; B = 8'b10101101; Cin = 1'b0; #10;

A = 8'b00100000 ; B = 8'b00100001; Cin = 1'b0; #10;

A = 8'b10101101 ; B = 8'b00101101; Cin = 1'b0; #10;

A = 8'b11101000 ; B = 8'b10100100; Cin = 1'b1; #10;

A = 8'b00100100 ; B = 8'b01101101; Cin = 1'b0; #10;

A = 8'b10101101 ; B = 8'b00101101; Cin = 1'b0; #10;

$finish;

end

  

  

endmodule

// Simulation waveforms