Question

Write the Verilog code for a 12-bit shift register with ability to shift left or right, synchronized parallel load, asynchronous reset, and serial output? The register is able to load the 12-bit input value (at the positive edge of the clock) if the load signal is one, shift the value in register one bit to the right (at the positive edge of the clock) if the rss signal is one, shift the value in register one bit to the left(at the positive edge of the clock) if lss signal is one, and reset the value in the register at any time if the rst signal is one. The shift register has two 1-bit output which are the MSB (Most significant bit) and LSB (Least significant bit) of the register at any given time. The priority of the signals is in the order as follows with rst having the highest priority. rst, load, rss, lss. When shift register is shifting the value to the right, the MSB bit takes in the load input MSB bit. When shift register is shifting the value to the left, the LSB bit takes in the load input LSB bit.

Answer 1

The working code of the above problem is written which is simulated also and verified for correct operation - I have a small suggestion in the problem statement that when the register is shifting towards right MSB bit will become zero so there is no point in tracking MSB bit. Similarly, for lest shift operation, this implies. BUT THE CODE I HAVE WRITTEN IS ACCORDING TO PROBLEM STATEMENT ONLY. So no need to worry about that.

If you want to make changes you can make any change d[0] to d[11] in last second line of code.

I have also written the comment in the code for better understanding (//)

written code - again

module shift_reg(data,clk,rst,load,rss,lss,msb,lsb);
input [11:0]data;
input clk;
input rst,load,rss,lss;
output reg msb,lsb;
reg [11:0]d;
reg [1:0]z;

always @(*) // Priority encoder which assigns priority accordingly to rst>load>rss>lss
begin
if(rst == 1)
z = 2'b11;
else if(rst == 0 && load == 1)
z = 2'b10;
else if(rst == 0 && load == 0 && rss == 1)
z = 2'b01;
else if(rst == 0 && load == 0 && rss == 0 && lss == 1)
z = 2'b00;
else
z = 2'bzz;
end

always @(*) // asynchronous reset without waiting for the clock posedege
begin
if(z == 2'b11)
begin d = 12'b0;
lsb = 0; msb = 0;
end
end

always@ (posedge clk)
begin
case(z)
2'b10: d = data; // loading the value of the load_data

2'b01: begin msb = d[11]; d = d>>1; end // assigning MSB bit of load to MSB_out
// as well as shifting the register
2'b00: begin lsb = d[0]; d = d<<1; end // assigning LSB bit of load to LSB_out
// as well as shifting the register to left
endcase
end
endmodule

If any more query you have you can comment in the comment section I am always ready to help