Question

(7494) Design and implementation of 4 bit shift register using Behavioral style of modeling .... by VHDL .. the program should based on the data sheet of 7494 and the truth table ... 13 input and one output D.

Answer 1

4-bit Shift Register Behavioral Code

entity ShiftReg4bit_beh is
Port ( Din,clk,reset : in STD_LOGIC;
Q : out STD_LOGIC_VECTOR (3 downto 0));
end ShiftReg4bit_beh;
architecture Behavioral of ShiftReg4bit_beh is
signal Q_temp: std_logic_vector(3 downto 0);
begin
Process(clk,reset)
begin
if(reset='1')then
Q_temp<="0000";
elsif(clk'event and clk='1')then
Q_temp<= Din & Q_temp(3 downto 1);
end if;
end process;
Q <= Q_temp;
end Behavioral;