A simple accelereometer GUI to calculate velocıty and displacement.
How can ı do thıs project ?

Flip-flops:
a) Make a asyncronous MOD 12 flip-flop up counter circuit
b) Make a asyncronous MOD 14 flip-flop up counter circuit
c) Each flip-flop has the same propagation delay, which is 10ms. Calculate the maximum clock frequency of the circuit in questions (a) and (b)

In propagation delay concept, what do Hold time and Setup time mean? (describe with an example)

Design a distribution system

simply explain with figure how electricity is transferred from Generating point to homes.

Q3). A 10KW, 415V, 50Hz, 4 pole, Y (star)-connected induction motor is running at 1425 rpm and is delivering full load output while operating at 89% efficiency.

a) Find the total losses of the motor [4 marks]

b) If the Copper loss, Core loss and Rotational loss are at a ratio of 1:0.7:0.2, find each loss separately [6 marks]

c) What is the torque output of the motor? [4 marks]

d) If the full load power factor is 0.85, what is the current drawn by the motor? [4 marks]

e) Find the phase voltage and phase current of the motor? [6 marks]

f) Find the full load slip of the motor? What will be running speed of the motor if the frequency is changed to 40 Hz assuming the operating slip remains the same? [6 marks]

g) Find the running cost of the motor for a year if the duty is 50% and cost of electricity is 30c per unit [4 marks]

what is a control Circuit ?
give real applications on control Circuit

What are the SHDN, LNA in opamp
What are the TXCO
coding algorithm for binary and target search in bitwise modulated signal I and Q?

question in telecom --------------

calculate an approximate for the average Error probability of a Bpsk system in an AWGN channel with zero mean and variance power spectral density equals to ((N0 over 2 ))

some hints

generation and detection block diagram- transmitter and receiver block diagram are related to this question

Use D flip-flops and gates to design a binary counter with each of the following repeated binary sequences: (a) 1, 5, 7 (b) 0, 2, 4, 6

(a) Draw the logic diagram (b) Construct Verilog RTL representation for the logics with verification.

delta to wye transformer. with the following voltages what is the phase to ground voltage.
A: 345kv
B: 115kv
C: 34kv
D: 12kv

do the same voltages for wye to delta, delta to delta and wye to wye transformer.
please show your work. so i could understand the math behind it.
thank you.

345kv primary to 115kv secondary
115kv primary to 34.5kv secondary
34.5kv primary to 12kv secondary