6 A 5 GHz signal is to be propagated in the dominant mode TE10 in a rectangular waveguide. If its group velocity is to be 90% of that of light. As engineer suggest i. What must be the dimensions of the waveguide (assume the standard waveguide)? ii. What impedance will the waveguide present to this signal if it is correctly matched?

Design a PLC ladder logic program to control a stop light. The program should have 3 outputs: RED, YELLOW, and GREEN. The ladder logic should illuminate green for 60 seconds, then yellow for 10 seconds, then red for 60 seconds. The system should also have two sensor inputs: THROUGH_TRAFFIC and CROSS_TRAFFIC which detect when there is through traffic and cross traffic present. If through traffic is detected, and no cross traffic is detected, the system should maintain a green light even after the green has remained lit for 60 seconds.

Consider a sequential circuit to control the washer:

The circuit receives 3 input signals: Clock, DoorOpen, and Start. It also maintains a state bit Wash.

If DoorOpen = 1, Wash should be set to 0.

Otherwise, if Start = 1, Wash should be set to 1 and if Start = 0, Wash should retain its value from previous cycle.

Make A truth table to compute the new value of Wash;

Make A circuit Diagram.

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How would the truth table look for this problem? I'm confused about how the state bit works with the table.

Here's my first attempt:

I don't know if this is right, let me know what is wrong with this.

Assume that you have a clock signal with frequency of 50 Hz, and you want to divide this signal into a frequency of 1 Hz signal. The counter chips you must use are synchronous decade (MOD 10) counter chips 74160 and synchronous MOD 16 counter chips 74161. Please use the back side of this paper to draw your circuit diagram with all the details.

You can use counter frequency division method to step down a higher frequency signal to a lower frequency signal. To divide a 50 Hz signal into a 1 Hz signal, you need to construct a counter with a total MOD 50 so that 50/50 = 1. To construct such a counter, you can use counter cascading method by cascading a MOD 10 counter such as 74160 with a MOD 5 counter so that the total MOD of the cascaded counter is 10x5 = 50. Since MOD 10 counter 74160 is a synchronous counter, you should truncate a synchronous counter such as a MOD 16 synchronous counter 74161 into a synchronous MOD 5 counter. You can use any additional logic gates in your counter truncation design.

(TCO 2) Describe the “Examine If Closed” instruction and provide an example of a physical component with a normal status that will make the instruction true.

(TCO 2) Describe how PLCs detect whether a switch is open or closed.

The following given set of data shows a set of 15-minute kW demands for four customers over a 24-hour period. A 25kVA single-phase transformer serves all the customers.

(a) Find the maximum 15-minute demand for each customer and the average 15-minute demand for each customer

(b) Find the total kWh usage and the load factor for each customer.

(c) For the 25kVA transformer, compute the maximum 15-minute coincident demand, the maximum 15-minute non-coincident demand and the load diversity.

1. Give an explanation with block diagram of microcomputer and microprocessor. What are the differences between microcomputer and microprocessor?

2. List FIVE (5) categories of the register. Describe each of it.

The voltage drop across an RLC circuit is:

v(t) = G*311.13*sine(377t) + 124.45*sine(1131t + 20) volts.

The current in the direction of the voltage drop is:

i(t) = 15.56*sine(377t) + 0.5*sine*(1131t - Φ)

Calculate:

a) The constants R, L, C of the circuit.
b) The angle value Φ
c) The average value of the power delivered to the circuit.

MATLAB

Write a user defined function for a projectile motion. If a ball is launched from initial position(0,0) with a velocity v0 at angle θ, determine your horizontal and vertical position. Please plot x vs. t, y vs. t and y vs. x.

Design in VHDL a 16-1 Demultiplexer

Screenshot the simulation and code.

Design in VHDL a 8-1 Multiplexer

Screenshot the simulation and code.

Assume that for a given program 70% of the executed instruction are arithmetic, 10% are load/store, and 20% are branch.
i. Given the instruction mix and the assumption that an arithmetic instruction requires 2 cycles, a load/store instruction takes 6 cycles, and a branch instruction takes 3 cycles, ?nd the average CPI.
ii. For a 25% improvement in performance, how many cycles, on average, may an arithmetic instruction take if load/store and branch instructions are not improved at all.

W6D

Begin by researching the electrical inspection requirements for commercial buildings in your locale.

In your response, describe the regulations that inspection agencies in your community have put in place for commercial buildings. How do these regulations differ across various electrical systems?