Question

Please list and describe the THREE major parts of a VHDL program. Describe each of them and give an example.

Answer 1

Three major parts of a VHDL program are:

(i) Entity Declaration (ii) Architecture declaration and body (iii) Process block

Additional there are configuration and pakage block.

(i) Entity declaration: It defines the I/O inteface of the intended design or RTL block. It consists of ports declaration of various width and data types like std_logic, std_logic_vector, bit types etc. Direction of data flow on these ports are defined as IN/OUT/INOUT/BUFFER type.

(ii) Architecture declaration: Entity declaration defines only external I/O's of the design where as architecture declares the internal relationship between the output signals and input signals. An architecture body can define the internal organization or function of the entity. Architecture comprises of two parts - declaration & concurrent statements. Declarative part of architecture contains signal, data types, functions, procedure, components etc. declarations whereas concurrent statements are of three types - Behavioral, data flow or structural.

Behavioral type of architecture body only describes expected functionality without any information about hardware where as data flow type consists of signal assignments. A structural model is based on component instantiation and generate statements. A mixed design of behavioral, data flow and structural too can be be used.

(iii) Process : Behavioral description of an entity is supported by process statements. Process statements are sequential in nature and executed in the order they are written. A process may contain sensitive list of signal which initiates execution of sequential statements. Wait statements are used if sensitive list is absent in the process body.

Example: Design of a Two bit full adder using 1 bit full adder. (Structural)

library ieee;

use ieee.std_logic_1164.all --- used to declare all functions to be used in the program

entity fulladder_1bit is

port (a, b, cin : in std_logic;

sum, cout : out std_logic

);

end fulladder_1bit;

architecture arch of fulladder_1bit is

begin ------------- data flow model

sum <= a xor b xor cin;

cout <= ( a and b) or (b and cin) or (a and cin);

end arch;

-------------------------------------------------------------------------------------------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all     

entity fulladder_2bit is

port ( x, y : in std_logic_vector (1 downto 0);

ci : std_logic;

s : out std_logic_vector(1 downto 0);

co: out std_logic

);

end fulladder_2bit;

architecture struct of fulladder_2bit is

signal c: std_logic;

component fulladder_1bit is

port (a, b, cin : in std_logic;

sum, cout : out std_logic

);

end component;

begin

----------structural describtion by instantiation

u0: fulladder_1bit port map (x(0), y(0), ci, s(0), c);

u1: fulladder_1bit port map (x(1), y(1), c, s(1), co);

end struct;