For a given Direct Current (DC) Machine:
3. Draw an equivalent circuit and list down all the losses that occur in DC motors.
4. Sketch a typical torque speed curve for a series motor.
5. Propose two methods to control the torque of a DC motor.

A complete wave rectified signal of peak 18V is injected into a capacitor filter . what is the value of the regulation of the filter if the output is a tension of 17 Vcc with full load ?

A three phase transformer of 200MVA, 33kV/380kV, Yd11 is delivering nominal power at cosφ = 1.

1. Calculate the nominal primary and secondary line current.
2. Calculate the winding ratio n of this transformer.

The primary line current is 15,9A during an open circuit test. The measured power per phase is then 53kW. During a short circuit test (at nominal current), 271V primary line voltage is measured at cosφ = 0,225.

3. Calculate the total iron losses and total copper losses of this transformer.
4. Calculate the total iron losses if the transformer would be connected to 16,5kV (primary side).
5. Draw the single-phase equivalent circuit of this transformer. Give also the phase quantities of the voltages and currents and indicate what the circuit elements represent.

Please show process and computations with comments.

A load draws between 100mA and 400mA at 6V. It is receiving power from an unregulated DC power supply whose output voltage can vary between 8.5V and 12V. Design a Zener diode voltage regulator using a 6V Zener diode that regulates for diode currents greater than 4mA and has a maximum power rating of 6W. Show the circuit diagram for the completed design and specify the power rating for all components.

Z- transformation Questions

Q1: given a difference equation, how do we find unit step/ impulse response?

Q2: based on Q1, do we need to find transfer function to get output response y(z)= h(z)x(z)

Q3: is initial condition for input x(z) =0 or is it given
Example: y(z)+2z^-1 y(1) = x(z) +2zx(1) + x(0)

if given y(1) =1, and x(1) and x(0) not given
do we assume x(1) and x(0) =0?

Code a 2:4 decoder with registered out. Also write a testbench of the decoder.

Write a Verilog HDL module that has three inputs, A, B, C, and one output, Y, to implement a function that Y output is true if at least two of the inputs are false

Also, write a testbench for the function.

A type K thermocouple with a 0°C reference will monitor an oven temperature at about 300°C. Vout was solved to equal 12.209mV. But part 2 I need help with.

Part 2 asks: Extension wires of 1000ft length and 0.01ohms/ft will be used to connect to the measurement site. Determine the minimum voltage measured input impedance if the error is to be within 0.2%?
The answer given is: 9.98kohms

The water surface of the reservoir is at an elevation of 326 m. A penstock with a length of 6.4 km supplies water

from the reservoir to a power plant at an elevation of 18m above sea level. If the turbine inlet pressure is 2.4 MPa,

estimate the head losses in the penstock.

Tests were carried out on a three-phase 220 V, 50 Hz, 4-pole delta-connected induction motor. The following results were obtained from open circuit (no-load) and short circuit tests.

            Open Circuit (no-load) Test

            Short Circuit (locked rotor) Test

            A dc resistance test indicates that the stator resistance per phase is 1.165 W.

a)        Estimate the machine’s friction and windage loss and determine the parameters of the full equivalent circuit of the machine.

Using an appropriate form of the machine equivalent circuit:

b)         Calculate the losses in the machine and draw a power flow diagram which illustrates the flow of power through the machine when it runs on-load with a slip of 0.06

c)         Determine the starting torque, and also the torque when running with a slip of 0.06.

1. What is the importance of power factor in the supply system ?

2. Why is the power factor not more than unity ?

3. What is the effect of low power factor on the generating stations ?

4. Why is unity power factor not the most economical p.f. ?

5. Why a consumer having low power factor is charged at higher rates ?

Design a 4-bit up/down counter which displays its output on the the 7-led segment using the decoder used in Lab 2.

In this lab, you will design a 4-bit up/down counter which displays its output on the 7-segment LED using the decoder that you designed in Lab 2.
The 4-bit up/down counter module has 4 inputs, Clk_1Hz, Reset, Pause, and Up; and a 4-bit output Count. If Reset is 1, the counter should reset its count value to zero (0000). If Reset is 0 and Pause is 1, the counter should pause and continue displaying the current count value. Otherwise, if Up is 1, on every clock cycle the counter should count up by one number. If Up is 0, the counter should count down on every clock cycle.
Upon reaching the minimum (0000) or maximum (1011) count, the counter value should wraparound. For example, when counting up, the counter should wraparound to 0000 after 1011, and when counting down, the counter should wraparound to 1011 after 0000. Reset has priority over Pause, which in turn has priority over counting up or down.
As in Lab 2, the left 8 switches should control which digits are on or off. This time, the rightmost switch will connect to Up; your counter should count up if this switch is up, and down if this switch is down. Connect BTNL to Pause, BTNR to Reset, and BTND to ClkDiv_Reset (the reset input to the ClkDiv module).
Lab Procedure and Demo: 1. Behaviorally design the 4-bit Up/Down Counter to operate as specified in the Lab Overview above. This is a behavioral design, not a structural design, so you may use if/else or case statements or any other Verilog statement that you want in the Counter module. You can read about these statements in chapter 6 of Verilog for Digital Design. You will also need to create your own Counter_Top module. You may modify any of the downloaded files or your own 7-segment display module as desired. 2. Create a testbench to test your design for correct functionality. At a minimum, the testbench should test the following cases: a. Check that counter counts up then down correctly b. Check for correct wraparound functionality for counting up and down c. Check for correct reset behavior from non-one count value d. Check for correct pause behavior e. Check that Reset has priority over Pause Your testbench module does not need to generate Tcl Console outputs; your simulation only needs to generate waveforms for this lab. You do not need to include the ClkDiv1Hz or Counter4_Top modules when you simulate a response with your testbench program. You do need to generate a signal for the clock input to your counter module. 3. Modify “Nexys4DDR_Master.xdc” as in Lab 2 to enable all 16 switches, and all 8 seven-segment displays on the FPGA board. Also, uncomment the two lines under the “## Clock signal” heading, and the lines for BTNL, BTNR, and BTND under the “##Buttons” heading. Synthesize, download and test your design on the Nexys4 FPGA board for correct functionality. At a minimum, you should test the same cases as your testbench. Demonstrate the correct behavior to your instructor. As in Lab 2, it may be easier to do this step before step 2.