Question

Design a 4-bit up/down counter which displays its output on the the 7-led segment using the decoder used in Lab 2.

In this lab, you will design a 4-bit up/down counter which displays its output on the 7-segment LED using the decoder that you designed in Lab 2.
The 4-bit up/down counter module has 4 inputs, Clk_1Hz, Reset, Pause, and Up; and a 4-bit output Count. If Reset is 1, the counter should reset its count value to zero (0000). If Reset is 0 and Pause is 1, the counter should pause and continue displaying the current count value. Otherwise, if Up is 1, on every clock cycle the counter should count up by one number. If Up is 0, the counter should count down on every clock cycle.
Upon reaching the minimum (0000) or maximum (1011) count, the counter value should wraparound. For example, when counting up, the counter should wraparound to 0000 after 1011, and when counting down, the counter should wraparound to 1011 after 0000. Reset has priority over Pause, which in turn has priority over counting up or down.
As in Lab 2, the left 8 switches should control which digits are on or off. This time, the rightmost switch will connect to Up; your counter should count up if this switch is up, and down if this switch is down. Connect BTNL to Pause, BTNR to Reset, and BTND to ClkDiv_Reset (the reset input to the ClkDiv module).
Lab Procedure and Demo: 1. Behaviorally design the 4-bit Up/Down Counter to operate as specified in the Lab Overview above. This is a behavioral design, not a structural design, so you may use if/else or case statements or any other Verilog statement that you want in the Counter module. You can read about these statements in chapter 6 of Verilog for Digital Design. You will also need to create your own Counter_Top module. You may modify any of the downloaded files or your own 7-segment display module as desired. 2. Create a testbench to test your design for correct functionality. At a minimum, the testbench should test the following cases: a. Check that counter counts up then down correctly b. Check for correct wraparound functionality for counting up and down c. Check for correct reset behavior from non-one count value d. Check for correct pause behavior e. Check that Reset has priority over Pause Your testbench module does not need to generate Tcl Console outputs; your simulation only needs to generate waveforms for this lab. You do not need to include the ClkDiv1Hz or Counter4_Top modules when you simulate a response with your testbench program. You do need to generate a signal for the clock input to your counter module. 3. Modify “Nexys4DDR_Master.xdc” as in Lab 2 to enable all 16 switches, and all 8 seven-segment displays on the FPGA board. Also, uncomment the two lines under the “## Clock signal” heading, and the lines for BTNL, BTNR, and BTND under the “##Buttons” heading. Synthesize, download and test your design on the Nexys4 FPGA board for correct functionality. At a minimum, you should test the same cases as your testbench. Demonstrate the correct behavior to your instructor. As in Lab 2, it may be easier to do this step before step 2.

Answer 1

the Verilog module

// Code your design here
module dut(clk,reset,pause,up_down,count);
input clk,reset,pause,up_down;
output reg [3:0] count;
always@(posedge clk)
begin
if(reset)
begin
count<=0;
end
else
if(pause)
begin
count<=count;
end
else
begin
if(up_down)
begin
if(count == 4'b1101)
begin
count<=0;
end
else
count<=count+1;
end
else
begin
if(count == 0)
begin
count<=4'b1101;
end
else
count<=count-1;
end
end
end
endmodule

// Code your testbench here
// or browse Examples
module test_counter();
reg clk,reset,pause,up_down;
wire [3:0] count;
dut d1(clk,reset,pause,up_down,count);
initial
begin
clk=0;reset=0;pause=0;up_down=1;
#2 reset=1;
#4 reset=0;pause=0;
#40 up_down=0;
#40 pause=1;
#4 pause=0;
#10 $finish;
end
initial
forever
#2 clk=~clk;
initial
$monitor("reset=%b pause=%b up_down=%b count=%b",reset,pause,up_down,count);
initial
begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
endmodule

waveform: