Design a 32 bit adder using a single 4 bit adder using verilog code

Expert Solution

module 32_bit_adder(input [31:0] A,input [31:0] B,input Cin,output [31:0] S,output Cout);
    wire C1, C2, C3, C4, C5, C6, C7;
    4_bit_adder ad0 (A[3:0], B[3:0], Cin, S[3:0], C1);
    4_bit_adder ad1 (A[7:4], B[7:4], C1, S[7:4], C2);

    4_bit_adder ad2 (A[11:8], B[11:8], C2, S[11:8], C3);
    4_bit_adder ad3 (A[15:12], B[15:12], C3, S[15:12], C4);

    4_bit_adder ad4 (A[19:16], B[19:16], C4, S[19:16], C5);
    4_bit_adder ad5 (A[23:20], B[23:20], C5, S[23:20], C6);

    4_bit_adder ad6 (A[27:24], B[27:24], C6, S[27:24], C7);
    4_bit_adder ad7 (A[31:28], B[31:28], C7, S[31:28], Cout);

endmodule

//1 bit full adder...

module full_adder(input A,input B,input Cin,output S,output Cout);
    assign S = A ^ B ^ CIN;
    assign COUT = (A & B) | (CIN & (A ^ B));
endmodule     //end 1 bit full adder...
//4 bit full adder...
module 4_bit_adder(input [3:0] A,input [3:0] B,input C0,output [3:0] S,output C4);
    wire C1, C2, C3;
    full_adder fu0 (A[0], B[0], C0, S[0], C1);
    full_adder fu1 (A[1], B[1], C1, S[1], C2);

    full_adder fu2 (A[2], B[2], C2, S[2], C3);
    full_adder fu3 (A[3], B[3], C3, S[3], C4);

endmodule    //end of 4 bit full adder...

Manojponduru answered 1 year ago

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