Question

Create a VHDL code of a 4 bit Counter using D flip flop and a Frequency Divider that provides the clock signal input for counter

Answer 1

Truth Table of 4-bit UP Counter

PRESENT STATE				NEXT STATE
Q3	Q2	Q1	Q0	Q3+	Q2+	Q1+	Q0+
0	0	0	0	0	0	0	1
0	0	0	1	0	0	1	0
0	0	1	0	0	0	1	1
0	0	1	1	0	1	0	0
0	1	0	0	0	1	0	1
0	1	0	1	0	1	1	0
0	1	1	0	0	1	1	1
0	1	1	1	1	0	0	0
1	0	0	0	1	0	0	1
1	0	0	1	1	0	1	0
1	0	1	0	1	0	1	1
1	0	1	1	1	1	0	0
1	1	0	0	1	1	0	1
1	1	0	1	1	1	1	0
1	1	1	0	1	1	1	1
1	1	1	1	0	0	0	0

D Flip Flop input expression using Karnaugh Mapping:

We use structural design approach. Separate modules for clock divider, d flip flop and top modules is shown below.

--Clock divider

library ieee;
use ieee.std_logic_1164.all;

entity clk_divider is
   port (   clock   : in std_logic;
       d_clock   : out std_logic
   );
end clk_divider;

architecture arch of clk_divider is

signal reg : integer := 0;

signal clkout : std_logic := '0';

begin

process (clock)
begin

   if rising_edge (clock) then
       if (reg = 16) then
           reg    <= 0;
           clkout    <= not clkout;
       else
           reg <= reg + 1;
       end if;
   end if;

end process;

d_clock <= clkout;

end arch;

--------------------------------------------------------------------------------------------------------------------------------------

--D Flip Flop

library ieee;
use ieee.std_logic_1164.all;

entity dff is
   port (   clock   : in std_logic;  
       d   : in std_logic;
       clr   : in std_logic;
       Q   : out std_logic
   );
end dff;

architecture arch of dff is

signal reg : std_logic := '0';

begin

process (clock, clr)

begin
   if (clr = '0') then

       reg <= '0';

   else

       if rising_edge(clock) then

           reg <= d;  
      
       end if;

   end if;  
  
end process;

Q <= reg;

end arch;

----------------------------------------------------------------------------------------------------------------------------------

--Top Design

library ieee;
use ieee.std_logic_1164.all;

entity counter is
   port (   clock   : in std_logic;
       clear   : in std_logic;
       Q   : out std_logic_vector(3 downto 0)
   );
end counter;

architecture structural of counter is

component clk_divider is
   port (   clock   : in std_logic;
       d_clock   : out std_logic
   );
end component;

component dff is
   port (   clock   : in std_logic;  
       d   : in std_logic;
       clr   : in std_logic;
       Q   : out std_logic
   );
end component;

signal d : std_logic_vector(3 downto 0);

signal din : std_logic_vector(3 downto 0);

signal dclk: std_logic;

begin

   din(0) <= not d(0);
   din(1) <= d(1) xor d(0);
   din(2) <= (not d(2) and d(1) and d(0)) or (d(2) and not d(0)) or (d(2) and not d(1));
   din(3) <= (d(3) and not d(2)) or (d(3) and not d(1)) or (d(3) and not d(0)) or (not d(3) and d(2) and d(1) and d(0));

   uut : clk_divider port map (clock, dclk);

   uut0 : dff port map (dclk, din(0), clear, d(0));
   uut1 : dff port map (dclk, din(1), clear, d(1));
   uut2 : dff port map (dclk, din(2), clear, d(2));
   uut3 : dff port map (dclk, din(3), clear, d(3));

   Q <= d;

end structural;

  
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--Simulated on ModelSim