In: Computer Science
Describe in behavioral VHDL a modulo-m up/down counter with the following interface:
– Generics
• Modulo base (m with default value of 16)
– Inputs
Clock (clk 1 bit)
Asynchronous reset (rst 1 bit)
Counting direction (up_down1 bit)
– 1Counting up
– 0Counting down – Outputs
2 – Run behavioral simulation
• Count value (count
• In Vivado
– Create a project
bits)