Question

In: Computer Science

Describe in behavioral VHDL a modulo-m up/down counter with the following interface: – Generics • Modulo...

Describe in behavioral VHDL a modulo-m up/down counter with the following interface:

– Generics
• Modulo base (m with default value of 16)

– Inputs

  • Clock (clk  1 bit)

  • Asynchronous reset (rst  1 bit)

  • Counting direction (up_down1 bit)

    • – 1Counting up

    • – 0Counting down – Outputs

2 – Run behavioral simulation

• Count value (count

• In Vivado
– Create a project

  bits)

Solutions

Expert Solution

VHDL code for the up-down counter

Testbench VHDL code for the up-down counter:


Related Solutions

Using behavioral VHDL, 32-bit up counter with enable.
Using behavioral VHDL, 32-bit up counter with enable.
Using Behavorial VHDL, design a 4-bit up/down counter.
Using Behavorial VHDL, design a 4-bit up/down counter.
Write VHDL code (behavior model) to implement a 4-bit modulo-9 counter and simulate your VHDL code...
Write VHDL code (behavior model) to implement a 4-bit modulo-9 counter and simulate your VHDL code of 4-bit modulo-9 counter in ModelSim, and capture the screenshot of your simulated waveform. Assume clock period Tclk=100ns, initially, the counter is reset to Q3Q2Q1Q0=0000 you need to simulate a complete counting cycle plus one more additional clock period after it is reset to “0000” state.
write sample code in VHDL Design and implementation of Pressetable ripple counter using behavioral style of...
write sample code in VHDL Design and implementation of Pressetable ripple counter using behavioral style of modeling by using pic74196
SOLVE FOLLOWING a.   Desgin and VERILOG code of a 3 bit up down counter USING T...
SOLVE FOLLOWING a.   Desgin and VERILOG code of a 3 bit up down counter USING T FLIP FLOP..... b. using behavioural module.Write a verilog discription of an N-BIT up down binary counter. Record the simulation output waveform in observation.....
Design a synchronous up down counter with the following binary sequence 1, 2, 4,5,7 using J-K...
Design a synchronous up down counter with the following binary sequence 1, 2, 4,5,7 using J-K Flip Flop
I need a design of Up/Down Logic Counter Brief information about the techniques to be used...
I need a design of Up/Down Logic Counter Brief information about the techniques to be used in the experiment will be given. The stages of the design problem and what will be done in these stages will be specified. (state diagram, state tables, state assignments, output and state equations, implementation with gates and flip flops and so on.) Material equipment list to be used in the implementation of the experiment will be provided. In the section where the test result...
Objective: Design, construct, and test a three-bit counter that counts up or down. An enable input...
Objective: Design, construct, and test a three-bit counter that counts up or down. An enable input E determines whether the counter is on or off.  If E=0, the counter is disabled and remains at its present count even though clock pulses are applied to the flip-flops.  If E=1, the counter is enabled and a second input, x, determines the direction of the count.  If x=1, the circuit counts upward with the sequence 000, 001, 010, 011, 100,...
Implement the synchronous 2-bit Up/Down counter with saturation at the end states. The flip-flop outputs Q1,...
Implement the synchronous 2-bit Up/Down counter with saturation at the end states. The flip-flop outputs Q1, Q0 serve as the outputs of the counter. The counting direction is set with mode control input M. With M =1 the flip-flop outputs follow the incrementing binary sequence starting from a current state with saturation at state 11 as shown in the following example: 00-> 01-> 10-> 11-> 11-> 11... With M =0 the outputs follow the decrementing binary sequence from a current...
Design a 4-bit up/down counter which displays its output on the the 7-led segment using the...
Design a 4-bit up/down counter which displays its output on the the 7-led segment using the decoder used in Lab 2. In this lab, you will design a 4-bit up/down counter which displays its output on the 7-segment LED using the decoder that you designed in Lab 2. The 4-bit up/down counter module has 4 inputs, Clk_1Hz, Reset, Pause, and Up; and a 4-bit output Count. If Reset is 1, the counter should reset its count value to zero (0000)....
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT