In: Electrical Engineering
create verilog source files for a seven segment
display using the software vivado.
show your steps.
module segmant_display7_display(
binary_coded_decimal,
segmant_display
);
//IO and Variable declarations.
input [3:0] binary_coded_decimal;
output [6:0] segmant_display;
reg [6:0] segmant_display;
always @(binary_coded_decimal)
begin
case
(binary_coded_decimal) //case statement
0 : segmant_display = 7'b0000001;
1 : segmant_display = 7'b1001111;
2 : segmant_display = 7'b0010010;
3 : segmant_display = 7'b0000110;
4 : segmant_display = 7'b1001100;
5 : segmant_display = 7'b0100100;
6 : segmant_display = 7'b0100000;
7 : segmant_display = 7'b0001111;
8 : segmant_display = 7'b0000000;
9 : segmant_display = 7'b0000100;
default : segmant_display = 7'b1111111;
endcase
end
endmodule