Question

Write and verify a behavioral Verilog model of J-K flip-flop with active-low asynchronous reset.

Answer 1

// Verilog behavioral model for J-K flipflop

module JK_ff (

//input port declarations

input clk,

input resetn,

input J,

input K,

  

//output port declarations

output Q ,

output Q_bar );

  

//internal signal declarations

reg Q_temp ;

  

//always block for JK flipflop operations

always @ (posedge clk or negedge resetn)

//jk flipflop triggered by positive edge of clock (clk)and has asynchronous active low reset (resetn)

begin

if (~resetn) //active low reset

Q_temp <= 1'b0;

else begin

case ({J,K})

2'b00: Q_temp <= Q_temp;//hold previous output

2'b01: Q_temp <= 1'b0;//reset

2'b10: Q_temp <= 1'b1;//set

2'b11: Q_temp <=(~Q_temp) ; //toggle previous output

endcase

end

end

  

//flipflop output logics

assign Q = Q_temp;

assign Q_bar = ~Q_temp;

  

endmodule

//verilog testbenh code for JK fliplfop

module test_JK_ff;

  

reg clk;

reg resetn;

reg J;

reg K;

  

wire Q;

wire Q_bar;

  

  

//instantiate DUT of JK_ff

JK_ff dut (.clk(clk),.resetn(resetn),.J(J),.K(K),.Q(Q),.Q_bar(Q_bar));

//clock generation

initial begin

clk = 1'b0;

forever #5 clk = ~clk;

end

  

//reset generation

initial begin

resetn = 1'b0;

#10 resetn = 1'b1;

end

  

//inpu stimulus generations

initial

begin

$dumpfile("dump.vcd");

$dumpvars(1);

J = 1'b0; K = 1'b0; #10;

J = 1'b0; K = 1'b1; #10;

J = 1'b1; K = 1'b0; #10;

J = 1'b1; K = 1'b1; #10;

J = 1'b1; K = 1'b0; #10;

J = 1'b0; K = 1'b0; #10;

J = 1'b0; K = 1'b1; #10;

J = 1'b1; K = 1'b1; #10;

J = 1'b0; K = 1'b0; #10;

  

#10 $finish;

end

endmodule

// Simulation waveforms