Question

Read sections in the TTL data sheets pertaining to the 74LS112A Dual J-K flip-flop.

1. For the 74LS112A, what is the maximum clock rate, minimum pulse width for the clock’s high and low levels, worst case propagation delay of the outputs from the high-to-low clock transition, and minimum input setup time?

2. Design a nine-step counter to count in the following sequence. Use J-K flip-flops, NAND gates, and Inverters only.

0011, 0101, 1001, 1000, 1011, 1010, 0110, 0100, 0111, 0011, …

Include in the design a means for resetting the counter to 0011.

Provide a circuit diagrams, relevant truth tables, state diagrams and state table.

In addition, provide the excitation functions for the J-K flip-flops.

Answer 1

1. Following are the data of 74LS112A for R_L = 2kohm, T_A = 25 degree Celcius, V_CC = 5V and for two different values of C_L

Parameter	CL = 15pF	CL = 50pF
Maximum clock rate	30MHz	25MHz
Minimum pulse width for clock high and low	20ns	25ns
Worst case propogation delay tPHL	20ns	28ns
Worst case propogation delay tPLH	20ns	24ns
Minimum setup time	20ns	25ns

2. Nine step counter

State diagram

State Table

Present State				Next State
QA	QB	QC	QD	QA+1	QB+1	QC+1	QD+1
0	0	0	0	0	0	1	1
0	0	0	1	0	0	1	1
0	0	1	0	0	0	1	1
0	0	1	1	0	1	0	1
0	1	0	0	0	1	1	1
0	1	0	1	1	0	0	1
0	1	1	0	0	1	0	0
0	1	1	1	0	0	1	1
1	0	0	0	1	0	1	1
1	0	0	1	1	0	0	0
1	0	1	0	0	1	1	0
1	0	1	1	1	0	1	0
1	1	0	0	0	0	1	1
1	1	0	1	0	0	1	1
1	1	1	0	0	0	1	1
1	1	1	1	0	0	1	1

Excitation table of JK Flipflop

Q	Q+	J	K
0	0	0	X
0	1	1	X
1	0	X	1
1	1	X	0

Including the J K inputs in the state table

Present State				Next State				Flip flop inputs
QA	QB	QC	QD	QA+1	QB+1	QC+1	QD+1	JA	KA	JB	KB	JC	KC	JD	KD
0	0	0	0	0	0	1	1	0	X	0	X	1	X	1	X
0	0	0	1	0	0	1	1	0	X	0	X	1	X	X	0
0	0	1	0	0	0	1	1	0	X	0	X	X	0	1	X
0	0	1	1	0	1	0	1	0	X	1	X	X	1	X	0
0	1	0	0	0	1	1	1	0	X	X	0	1	X	1	X
0	1	0	1	1	0	0	1	1	X	X	1	0	X	X	0
0	1	1	0	0	1	0	0	0	X	X	0	X	1	0	X
0	1	1	1	0	0	1	1	0	X	X	1	X	0	X	0
1	0	0	0	1	0	1	1	X	0	0	X	1	X	1	X
1	0	0	1	1	0	0	0	X	0	0	X	0	X	X	1
1	0	1	0	0	1	1	0	X	1	1	X	X	0	0	X
1	0	1	1	1	0	1	0	X	0	X	1	X	0	X	1
1	1	0	0	0	0	1	1	X	1	X	1	1	X	1	X
1	1	0	1	0	0	1	1	X	1	X	1	1	X	X	0
1	1	1	0	0	0	1	1	X	1	X	1	X	0	1	X
1	1	1	1	0	0	1	1	X	1	X	1	X	0	X	0

K - maps

Circuit Diagram