Question

2. Design a falling-edge triggered SR flip-flop with an active-high asynchronous clear.

a) Draw the logic symbol and a truth table.

b) Write a complete VHDL model (entity and behavioral architecture)

Answer 1

//-------------------VHDL CODE FOR ASYNCHRONOUS SR FLIFLOP--------///
library IEEE;
use IEEE.std_logic_1164.all;
use ieee. std_logic_arith.all;
use ieee. std_logic_unsigned.all;

entity sr_ff is
port(
     S,R,CLR,clk:in std_logic;
     Q,Q_bar:out std_logic);
     end sr_ff;

Architecture behavioural of sr_ff is
begin

process(clk)
begin

if(CLR='1') then
Q<='0';
end if;

if(clk='0' and clk'event)then
                                  //since it is falling edge triggered
if(S='0' and R='0') then
Q<=Q;
elsif(S='0' and R='1') then      //reset
Q<='0';
elsif(S='1' and R='0') then    //set state
Q<='1';
else
Q<='Z';              //if S=R=1 then it is indetermnate state
end if;
end if;
Q_bar<= not Q;        //generally q_bar is negation of Q

end process;
end behavioural;

(If you have any query leave a comment . Thank you)