Question

In: Electrical Engineering

Verify the operation of a D flip-flop by providing appropriate inputs to the D, Preset, and...

Verify the operation of a D flip-flop by providing appropriate inputs to the D, Preset, and Clear pins. Use CLOCK input to the flip-flop to function properly ( can be found under wiring in Logisim)

//If you present a diagram designed in the "Logisim app" it would be very much appreciated. Thank you

Solutions

Expert Solution

please note that the D flipflop in logisim have 'en" ( enable input) rather than preset , and the clock is effective to the flip flop only when en=1, it is different to preset actually, this is an important thing which have to considered and the clear input is active high here and  as we know it is asynchoronous that is doesn't depend upon the clock.

i) simulation result when clear is active

we can see that from the above simulation result that Q=0 as clear =1

ii) simulation result when clock applied and enabled i.e en=1 and clear inactive and D=0

we can see from the simulation result above that Q=0 as D=0 when clock applied.

iii) simulation result when clock applied and enabled i.e en=1 and clear inactive and D=1.

we can see from the simulation result above that Q=1 as D=1 when clock applied.


Related Solutions

Write the VHDL PROCESS statements for a D flip-flop with synchronous active-LOW clear, synchronous active-LOW preset,...
Write the VHDL PROCESS statements for a D flip-flop with synchronous active-LOW clear, synchronous active-LOW preset, and responsive to a rising edge clock. Use D for the input, Q for the output, PRE for the preset, CLR for the clear, and CLK for the clock. All signals are BIT type
9. Why is the D flip flop the more common flip flop? 10. What is the...
9. Why is the D flip flop the more common flip flop? 10. What is the purpose of a clock in a digital system?
You are to implement the following in VHDL: D flip-flop D flip-flop       with enable and reset J-K...
You are to implement the following in VHDL: D flip-flop D flip-flop       with enable and reset J-K flip flop with asynchronous set T Flip flop with asynchronous clear
A T flip-flop is a 1-bit synchronous storage component alternative to the D flip-flop, with a...
A T flip-flop is a 1-bit synchronous storage component alternative to the D flip-flop, with a slightly different interface. The T flip-flop has one input t to synchronously control the state of the flip-flop, as follows: When t is 0, the flip-flop does not change its state value. When t is 1, the flip-flop inverts its current state value (0 becomes 1, and 1 becomes 0). Write a Verilog module for the T flip-flop using a behavioral model. The flip-flop...
Design a synchronously settable flip-flop using a regular D flip-flop and additional gates.
Design a synchronously settable flip-flop using a regular D flip-flop and additional gates.
Imagine a new kind of flip-flop called a J N flip-flop which has two inputs J...
Imagine a new kind of flip-flop called a J N flip-flop which has two inputs J and N. Input J behaves like the J input of the J K flip-flop, and input N behaves like the complement of the K input of a J K flip-flop (N=K’). Derive the characteristic table and excitation table of the J N flip-flop. Show that a D flip-flop can be constructed from a J N flip-flop by connecting its two inputs (J and N)...
Write and verify a behavioral Verilog model of J-K flip-flop with active-low asynchronous reset.
Write and verify a behavioral Verilog model of J-K flip-flop with active-low asynchronous reset.
Create a VHDL code of a 4 bit Counter using D flip flop and a Frequency...
Create a VHDL code of a 4 bit Counter using D flip flop and a Frequency Divider that provides the clock signal input for counter
Create a state meachine that encrypts an incoming digital bitstream using a D-flip-flop and a Mealy...
Create a state meachine that encrypts an incoming digital bitstream using a D-flip-flop and a Mealy Meachine. The device have to meet these requirments: A. The output of the encryption device matches the input bitstream until a certain set of bits is detected (such as 110). After this detection, the output is the complemented version of the input. B. When a second bitstream 010 is detected, the output reverts to simply matching the input stream again. Please make both bitstreams...
Please no hand writing Start a new Quartus project for D flip-flop with enable, reset, set,...
Please no hand writing Start a new Quartus project for D flip-flop with enable, reset, set, cp. type the VHDL code create the circuits in Quartus.
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT