Question

Write a VHDL code and testbench for a positive-edge-triggered JK-type FF with asynchronous active-low reset (RN) - JKFFR

Answer 1

--VHDL code for J-K flipflop

library ieee;

use ieee.std_logic_1164.all;

--entity declaration for J-K flipflop

entity JK_FF is

port(

clk: in std_logic;

rst: in std_logic;

j: in std_logic;

k: in std_logic;

q: out std_logic;

q_bar: out std_logic );

end JK_FF;

--architecture declaration of J-K flipflop

architecture behavioral of JK_FF is

--internal signal declarations

signal q_reg :std_logic;

begin

process(clk,rst) -- asynchronous reset

begin

if(rst='0') then -- active low reset

q_reg <= '0';

elsif (rising_edge(clk)) then

if(j='0' and k='0') then

q_reg <= q_reg;

elsif(j='0' and k='1') then

q_reg <= '0';

elsif(j='1' and k='0') then

q_reg <= '1';

else q_reg <= (not q_Reg);

end if;

end if;

end process;

q <= q_reg;

q_bar <= (not q_Reg);

end behavioral;

-- VHDL testbench code J-K flipflop

library IEEE;

use IEEE.std_logic_1164.all;

--entity declaration for testbench

entity test_JK_FF is

end test_JK_FF;

--architecture body declaration for testbench

architecture behavioral of test_JK_FF is

--component declaration for JK_FF

component JK_FF is

port(

clk: in std_logic;

rst: in std_logic;

j: in std_logic;

k: in std_logic;

q: out std_logic;

q_bar: out std_logic );

end component;

--internal signal declarations

signal clk,rst,j,k:std_logic;

signal q,q_bar:std_logic;

constant clk_period : time := 10 ns;

begin

--instantiate DUT

DUT: JK_FF port map (clk,rst,j,k,q,q_bar);

--clock stimulus

clk_process :process

begin

clk <= '0';

wait for clk_period/2;

clk <= '1';

wait for clk_period/2;

end process;

--input stimuls

stim_proc: process

begin  

rst <= '0';

j <= '0';

k <= '0';

wait for 15 ns;

rst <= '1';

j <= '0';

k <= '0';

wait for 20 ns;

  

rst <= '1';

j <= '0';

k <= '1';

wait for 20 ns;

  

rst <= '1';

j <= '1';

k <= '0';

wait for 20 ns;

  

rst <= '1';

j <= '1';

k <= '1';

wait for 20 ns;

rst <= '1';

j <= '0';

k <= '0';

wait;

end process;

END;

-- simulation waveforms