Question

Write the VHDL PROCESS statements for a D flip-flop with synchronous active-LOW clear, synchronous active-LOW preset, and responsive to a rising edge clock. Use D for the input, Q for the output, PRE for the preset, CLR for the clear, and CLK for the clock. All signals are BIT type

Answer 1

--library declaration for the module.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

--This is a D Flip-Flop with Synchronous Reset,Set and Clock Enable(posedge clk).

--Note that the reset input has the highest priority,Set being the next highest

--priority and clock enable having the lowest priority.

entity example_FDRSE is

port(

Q : out std_logic; -- Data output

CLK :in std_logic; -- Clock input

CE :in std_logic; -- Clock enable input

RESET :in std_logic; -- Synchronous reset input

D :in std_logic; -- Data input

SET : in std_logic -- Synchronous set input

);

end example_FDRSE;

architecture Behavioral of example_FDRSE is --architecture of the circuit.

begin --"begin" statement for architecture.

process(CLK) --process with sensitivity list.

begin --"begin" statment for the process.

if ( rising_edge(CLK) ) then --This makes the process synchronous(with clock)

if (RESET = '1') then

Q <= '0';

   else

if(SET = '1') then

Q <= '1';

else

if ( CE = '1') then

       Q <= D;

   end if;

       end if;

end if;

end if;

end process; --end of process statement.

end Behavioral;

--library declaration for the module.

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

--This is a D Flip-Flop with Synchronous Reset,Set and Clock Enable(posedge clk).

--Note that the reset input has the highest priority,Set being the next highest

--priority and clock enable having the lowest priority.

entity example_FDRSE is

port(

Q : out std_logic; -- Data output

CLK :in std_logic; -- Clock input

CE :in std_logic; -- Clock enable input

RESET :in std_logic; -- Synchronous reset input

D :in std_logic; -- Data input

SET : in std_logic -- Synchronous set input

);

end example_FDRSE;

architecture Behavioral of example_FDRSE is --architecture of the circuit.

begin --"begin" statement for architecture.

process(CLK) --process with sensitivity list.

begin --"begin" statment for the process.

if ( rising_edge(CLK) ) then --This makes the process synchronous(with clock)

if (RESET = '1') then

Q <= '0';

   else

if(SET = '1') then

Q <= '1';

else

if ( CE = '1') then

       Q <= D;

   end if;

       end if;

end if;

end if;

end process; --end of process statement.

end Behavioral;v