Question

using verilog to design a 8x8 unsigned multiplier(with testbench) utilizing a 2x8 multiplier as a building block

here is the testbench and code for 2x8:

module cpp_mult(mplr,mcand, prod);

input [1:0] mplr;

input [7:0] mcand;

output [9:0] prod;

wire [9:0] mcand1;
wire [9:0] mcand2;
wire [9:0] mcand3;

assign mcand0 = 10'b00000000;
assign prod = (mplr==2'b00)?mcand0 :
       ((mplr==2'b01)?{2'b00,mcand[7:0]}:
       ((mplr==2'b10)?{1'b0,mcand[7:0],1'b0}:
       ((mplr==2'b11)?{2'b00,mcand[7:0]}+{1'b0,mcand[7:0],1'b0}:8'hxx)));

endmodule

____________________________________________________________________

module cpp_mult_tb();
reg [1:0] mplr;
reg [7:0] mcand;
wire [9:0] prod;

// Instantiate the design under test (DUT). In this case it is cpp_mult.
cpp_mult U1 (mcand, mplr, prod);

initial // initial block executes only once
begin
mplr = 2'b00;
mcand = 8'h00;
#10;   
mplr = 2'b00;
mcand = 8'hFF;
#10;   
mplr = 2'b01;
mcand = 8'hFF;
#10;   
mplr = 2'b01;
mcand = 8'hFF;
#10;   
mplr = 2'b10;
mcand = 8'hFF;
#10;   
mplr = 2'b11;
mcand = 8'hFF;
#10;   
end

endmodule

Answer 1

There are errors in the code you given the question.Lets verify your code doing simulation it gives error.

The modification of your code is below.

Code:

module cpp_mult(mplr,mcand, prod);
input [1:0] mplr;
input [7:0] mcand;
output [9:0] prod;
wire [9:0] mcand1;
wire [9:0] mcand2;
wire [9:0] mcand3;
assign mcand0 = 10'b00000000;
assign prod = (mplr==2'b00)?mcand0 :
((mplr==2'b01)?{2'b00,mcand[7:0]}:
((mplr==2'b10)?{1'b0,mcand[7:0],1'b0}:{2'b00,mcand[7:0]}+{1'b0,mcand[7:0],1'b0}));
//((mplr==2'b11)?{2'b00,mcand[7:0]}+{1'b0,mcand[7:0],1'b0}:8'hxx)));

endmodule

code snippet:

Test Bench code:

module cpp_mult_tb();
reg [1:0] mplr;
reg [7:0] mcand;
wire [9:0] prod;
// Instantiate the design under test (DUT). In this case it is cpp_mult.
cpp_mult U1 (mplr,mcand, prod);
initial // initial block executes only once
begin
mplr = 2'b00;
mcand = 8'h00;
#10;   
mplr = 2'b00;
mcand = 8'hFF;
#10;   
mplr = 2'b01;
mcand = 8'hFF;
#10;   
mplr = 2'b01;
mcand = 8'hFF;
#10;   
mplr = 2'b10;
mcand = 8'hFF;
#10;   
mplr = 2'b11;
mcand = 8'hFF;
#10;   
end
endmodule

Code Snippet:

In your code you made a mistake in assignment statement .You used 8,bxx so while i simulate your code i got the output as xx only for all input combinations.

So i changed the condition once see into my code.

In the testbench while module instantiation you have to fallow the same order how you declared inputs and outputs in the module.But in your code the instantiation input and output places are not same as in the main module so i have changed that also.

Please see these changes in my code.

After these changes i get the output of the 2x8 multiplier output.

By using this code i designed 8x8 multiplier

8X8 multiplier Verilog code:

module multiplier_8x8(mplr,mcand, prod);
input [7:0] mplr; //inputs mplr and mcand are 8 bits
input [7:0] mcand;
output wire [15:0] prod;//product is 16 bit.
//Wire are all 10 bit which stores each 2X8 multiplier outputs
wire [9:0] mcand1;
wire [9:0] mcand2;
wire [9:0] mcand3;
wire [9:0] mcand4;
//2x8 multliplier module instantiation
cpp_mult c1(mplr[1:0],mcand, mcand1);
cpp_mult c2(mplr[3:2],mcand, mcand2);
cpp_mult c3(mplr[5:4],mcand, mcand3);
cpp_mult c4(mplr[7:6],mcand, mcand4);
//product assignment using partial outputs of 2x8 multipliers
assign prod=({6'b000000,mcand1}+{4'b0000,mcand2,2'b00}+{2'b00,mcand3,4'b0000}+{mcand4,6'b000000});
endmodule

code snippet:

The test bench code of 8x8 multiplier:

module multiplier_8x8_tb;
//In testbench inputs and outputs are declared as reg and wire respectively
reg [7:0] mplr;
reg [7:0] mcand;
wire [15:0] prod;
//8x8 mutliplier module instantiation
multiplier_8x8 m1(mplr,mcand, prod);
initial // initial block executes only once
//value assignments to the input
begin
mplr = 8'b00;
mcand = 8'h00;
#10;   
mplr = 8'b00;
mcand = 8'hFF;
#10;   
mplr = 8'b01;
mcand = 8'hFF;
#10;   
mplr = 8'b01;
mcand = 8'hFF;
#10;   
mplr = 8'b10;
mcand = 8'hFF;
#10;   
mplr = 8'b11;
mcand = 8'hFF;
#10;   
mplr = 8'd5;
mcand = 8'hFF;
#10;   
mplr = 8'd6;
mcand = 8'hFF;
#10;   
mplr = 8'd15;
mcand = 8'hFF;
end
endmodule

Code snippet:

Simulation Results:

This is the output for the some of the inputs.You can change the inputs in testbench.

I used vivado software for the simulation results.

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