In: Electrical Engineering

Please answer both the questions.

1 a) Design two bits comparators using Verilog description language

Note: Design means RTL code and Testbench covering all possible corner cases)

b)

How many latches will result when the following code is synthesized? Assume B is 4-bits long.

always@(state)

begin

case(state)

2’b00: B = 5;

2’b01: B = 3;

2’b10: B = 0;

endcase

end

**Verilog Code for the 2bit comparator is**

module comparator(input [1:0] A,B, output A_less_B, A_equal_B,
A_greater_B);

wire tmp1,tmp2,tmp3,tmp4,tmp5, tmp6, tmp7, tmp8;

// A = B output

xnor u1(tmp1,A[1],B[1]);

xnor u2(tmp2,A[0],B[0]);

and u3(A_equal_B,tmp1,tmp2);

// A less than B output

assign tmp3 = (~A[0])& (~A[1])& B[0];

assign tmp4 = (~A[1])& B[1];

assign tmp5 = (~A[0])& B[1]& B[0];

assign A_less_B = tmp3 | tmp4 | tmp5;

// A greater than B output

assign tmp6 = (~B[0])& (~B[1])& A[0];

assign tmp7 = (~B[1])& A[1];

assign tmp8 = (~B[0])& A[1]& A[0];

assign A_greater_B = tmp6 | tmp7 | tmp8;

endmodule

**Now the test bench for the above verilog code is given
as follows**

module tb_comparator;

reg [1:0] A, B;

wire A_less_B, A_equal_B, A_greater_B;

integer i;

// device under test

comparator dut(A,B,A_less_B, A_equal_B, A_greater_B);

initial begin

for (i=0;i<4;i=i+1)

begin

A = i;

B = i + 1;

#20;

end

for (i=0;i<4;i=i+1)

begin

A = i;

B = i;

#20;

end

for (i=0;i<4;i=i+1)

begin

A = i+1;

B = i;

#20;

end

end

endmodule

**Here I tried to cover all the test cases. And the
simulation result will look like :**

b. Here let's see why the latch will be created. We can see from the case statement if the case is state = 2b'11 then no case is defined and due to some external effects in the code then the value of state goes to 2b'11 then the code does not know where to change the B so it will retain its previous value. To retain the previous value the B value must be latched. B is of 4 bit but we can see that the MSB bit of B is always at zero and it is not changing. Therefor for the MSB bit no need to use any latch we can directly connect it to the ground and for other bits we have to use the latch to retain previous value. Finally 3 latches will be created for the above code snipit.

(Write/Design) both the RTL and Testbench using the Verilog HDL
language of the five input majority using the structure modeling
approach.
NOTE: Design means RTL code and Testbench covering all possible
corner cases

Design a circuit and write a verilog code description of the
16-bit right rotator using barrel shift method

Design a Verilog code for 64x64 array multiplier. Use behavioral
Verilog description with full adders and/or half adders. Please
include testbench

Using Behavioral model, write a Verilog description of
parameterized Multiplier:
1.Make one stimulus for two different parameter values and show
the wave forms
results.
2. Analyse the circuits implementation of Structural Binary
Multiplier and Behavioral-Level
Multiplier, in terms of resource utilization and critical path
delay (Input size should be
same).

note (Please solve the questions in the language of
operating systems)
[2] (i) Define
Timesharing.
(ii) In a one
processor system, there is an interrupt
clock which is set to a “time slice Q”, that is,
every Q an interrupt occurs to stop the process. There is only one
I/O device in the system which is interrupted
when the process needs an I/O. There are 3 processes A, B, C.
Process A executes an I/O interrupt
every...

Please answer these questions using SPSS. Thank you
Note: For all assignments, you must show the
requested output from SPSS.
Example. Determine the descriptive statistics
for three quantitative variables. Which variable has the highest
mean? The most variability?
Answer: Output should include 3 boxes of
descriptive statistics, one for each variable. There should also be
one page that gives the answer to the other two questions.
The following sample data are used. We are interested in the
descriptive statistics from...

Answer the following short questions and give a reason to
support your answer. Please note that no marks will be awarded if
you do not provide a reason to support your answer.
1. Give two situations in which you would recommend the sample
median over the sample mean as a measure of location.(Give
statistical comparison)
2. Is the sample mean always larger than the sample median for
skewed data?(Give graphic example)
3. Is it true that histograms are a more...

Please provide a digital design circuit modeled in
structural verilog that takes two 5-bit inputs (in
2's complement format), and a add/subtract input. If add/subtract =
0 than the circuits ouputs A+B, If add subtract = 1, the circuit
outputs A-B (by taking the 2's compliment of B and than
adding).
will upvote, thanks

Please answer both the questions
1) Describe the way the energy levels move as the depth is
reduced in a finite potential well and explain why they behave in
this manner.
2) Explain the change in energy levels, and explain the behavior
of the energy levels when the effective mass is increased.

Please answer both of the 2 multi-part questions:
1. 78% of people report that they are sleepy two hours after
they wake up. But you believe that among people who drink coffee,
this rate is lower.
1a) Determine the null and alternative hypothesis.
1b) What would it mean here to make a Type I error?
2. Write the hypotheses and the conclusion for this
situation:
It is published that a certain kind of light bulb has a mean
lifetime of...

ADVERTISEMENT

ADVERTISEMENT

Latest Questions

- Consider Neutrogena Corporation’s original strategy for producing and selling “kind to the skin” residue-free soap with...
- Patricia has been renting a two bedroom house for years. She pays $1000 per month in...
- Please discuss the following case study. In doing so, explain your approach to the problem and...
- Suppose x = 0x5A and y = 0xA5. What is the output for x | y?...
- Discuss the role of the FDA in the healthcare industry?
- Discuss the importance of boilerplate contract terms and conditions as part of the contract. How do...
- Real Madrid stadium requires seats for home and away end. The seating project results in $1.2...

ADVERTISEMENT