Question

Please answer both the questions.

1 a) Design two bits comparators using Verilog description language

Note: Design means RTL code and Testbench covering all possible corner cases)

b)

How many latches will result when the following code is synthesized? Assume B is 4-bits long.

                               always@(state)

                               begin

                                        case(state)

                                      2’b00: B = 5;

                                         2’b01: B = 3;

                                      2’b10: B = 0;

                                        endcase

                               end

Answer 1

Verilog Code for the 2bit comparator is

module comparator(input [1:0] A,B, output A_less_B, A_equal_B, A_greater_B);
wire tmp1,tmp2,tmp3,tmp4,tmp5, tmp6, tmp7, tmp8;

// A = B output   
xnor u1(tmp1,A[1],B[1]);
xnor u2(tmp2,A[0],B[0]);
and u3(A_equal_B,tmp1,tmp2);

// A less than B output   
assign tmp3 = (~A[0])& (~A[1])& B[0];
assign tmp4 = (~A[1])& B[1];
assign tmp5 = (~A[0])& B[1]& B[0];
assign A_less_B = tmp3 | tmp4 | tmp5;

// A greater than B output   
assign tmp6 = (~B[0])& (~B[1])& A[0];
assign tmp7 = (~B[1])& A[1];
assign tmp8 = (~B[0])& A[1]& A[0];
assign A_greater_B = tmp6 | tmp7 | tmp8;
endmodule

Now the test bench for the above verilog code is given as follows

module tb_comparator;
reg [1:0] A, B;
wire A_less_B, A_equal_B, A_greater_B;
integer i;
// device under test
comparator dut(A,B,A_less_B, A_equal_B, A_greater_B);
initial begin
for (i=0;i<4;i=i+1)
begin   
A = i;
B = i + 1;
#20;
end   
for (i=0;i<4;i=i+1)
begin   
A = i;
B = i;
#20;
end   
for (i=0;i<4;i=i+1)
begin   
A = i+1;
B = i;
#20;
end   
end   
endmodule

Here I tried to cover all the test cases. And the simulation result will look like :

b. Here let's see why the latch will be created. We can see from the case statement if the case is state = 2b'11 then no case is defined and due to some external effects in the code then the value of state goes to 2b'11 then the code does not know where to change the B so it will retain its previous value. To retain the previous value the B value must be latched. B is of 4 bit but we can see that the MSB bit of B is always at zero and it is not changing. Therefor for the MSB bit no need to use any latch we can directly connect it to the ground and for other bits we have to use the latch to retain previous value. Finally 3 latches will be created for the above code snipit.