Create the Decoder module in System Verilog to decode the 4-bit Binary Coded Decimal digit into...

Create the Decoder module in System Verilog to decode the 4-bit Binary Coded Decimal digit into seven-segment code. You can also include and instantiate your decoder schematic from Section 3 instead of writing a new System Verilog module.

Expert Solution

VERILOG CODE

module bcd_7segment(BCD,clk, segment);
input [3:0] BCD;
input clk; //inputs ABCD
output reg [6:0] segment; //segments abcdefg

always @ ( posedge clk)
begin
case (BCD)
    4'b0000 : begin segment = 7'b1111110; end   //BCD 0
4'b0001 : begin segment = 7'b0110000; end//BCD 1
4'b0010 : begin segment = 7'b1101101; end   //BCD2
4'b0011 : begin segment = 7'b1111001; end   //3
4'b0100 : begin segment = 7'b0110011; end   //4
4'b0101 : begin segment = 7'b1011011; end   //5
4'b0110 : begin segment = 7'b1011111; end   //6
4'b0111 : begin segment = 7'b1110000; end   //7
4'b1000 : begin segment = 7'b1111111; end       //8
4'b1001 : begin segment = 7'b1110011; end   //9
default : begin segment = 7'b0000000; end   //default 0
endcase
end
endmodule

Manojponduru answered 2 years ago

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Create the Decoder module in System Verilog to decode the 4-bit Binary Coded Decimal digit into...

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