Find the autocorrelation sequence for discrete signal c[n]=[=0.8,1.6,0,2.4,-4]. 0 is the origin. Graph each step and the sequence. Write the sequence also.

a) Design a16-bit MIPS Processor in a simplest form in Verilog code with testbench. Please mention the comments where applicable.

b) mention the steps how your design works.

List the Electric equipment used in Testing and Maintenance of Transformers. Discuss each equipment.

i am working on a project..
i would love to implement ENERGY METERING WITH IT SO AS TO BE ABLE TO CALCULATE THE BILLS AT THE END OF A CERTAIN PERIOD..
how could this be done...BULBS,FANS,SOCKETS are the appliances involved...
how can i get the energy used by all this appliances.

i need very DETAILED TECHNICAL EXPLANATION.

A Y- connected, 460- V, 1710- rpm, 60- Hz, 4- pole squirrel cage induction motor has a rotor current at starting 6 times the rotor current at full load. Calculate:

a. The starting torque as percent of full load torque.
b. The slip and speed at which the motor develops maximum torque.
c. The maximum torque developed b the motor as percent of its full load value.

Consider a BJT transistor acting as a switch. How to determine the design resistances if we want to transition between cut off and saturation region to active region?

Seven Segment display is applicable for alphanumeric display both . Suppose you are appointed as an engineer in company, which deals in same area (Seven Segment display unit) As per customer demand, you need to design a basic logic gate circuit diagram (Combinational circuit), which having output 1 (HIGH) when a 4-bit BCD code translated to a number that uses the upper ngt segment of a single seven segment display unit

Write instruction(s) in C to get bits 4 and 7 of Port-C, then compute the “XOR (exclusive OR)” of these two bits and write the result of the “XOR operation” to bit 4 of Port-D.

Determine the most economical size of a 3-phase line which supplies the following loads at 10 kV : (i) 100 kW at 0·8 p.f. (lag) for 10 hours (ii) 500 kW at 0·9 p.f. (lag) for 8 hours (iii) 100 kW at unity p.f. for 6 hours. The above gives the daily load cycle. The cost per km of the completely erected line is Rs (8000 a + 1500) where a is the area of cross-section of each conductor. The combined interest and depreciation is 10% per annum of capital cost. Cost of energy losses is 5 paise per kWh. Resistivity of conductor material = 1·72 × 10−6 Ω cm.

(A) Minimize the following Boolean expression as much as possible and Design the obtained function with NAND universal logic gates
Y = AB + A(B+C) + B (B+C)

(B) Design a logic gate circuit diagram ( combination circuit ) that accepts a 3 - bit BCD number and generates an output binary number equal to the square of input number.

You are to design two CONCEPUTALLY different synchronous state machines (Mealy and Moore) that perform the task described below. You are allowed to use any type of flip-flop. However, I recommend that you use either JK or D flip-flops. There is a game called screwball. Every time a ball is put into play either player 1 (P1) scores a point or player 2 (P2) scores a point. A winner is declared when one player is ahead by 2 points. Starting with a score of 0:0 for P1 vs. P2, a game might progress as follows: 0:1 1:1 2:1 3:1 (P1 Wins!) Design a finite state machine that uses information about which player scores a point at each stage of a game to determine when a player wins and which player wins. Your design should include one reset input to initialize your win announcer (this may be a synchronous or an asynchronous input, as you desire). The outputs from your designs should indicate BOTH when a win has occurred and which player is the winner. Hint: You design should have one input (Ball) and two outputs (Player 1 (P1) and Player 2 (P2))

Please Use Mealy State. Thank You!

What would be the wiring setup and coding using an Arduino for a display of the temperature of the room it is in?

Describe briefly with the aid of suitable diagrams the mechanism of the lightning
stroke generation.

8. What two circuits are used to generate the IF? (Intermediate Frequency)

62. The synthesizer in a transceiver usually generates what
frequencies?