Questions
Hello, i am currently working on an attendance system using MATLAB by the comparison of 2...

Hello, i am currently working on an attendance system using MATLAB by the comparison of 2 images of the same class, does anyone have any ideas or methods to use

In: Electrical Engineering

Consider a finite state machine with a control input called mode. When mode = 0, the...

Consider a finite state machine with a control input called mode. When mode = 0, the machine operates as a mod-3 down counter, where the outputs are the count values. When mode = 1, the machine's output progresses through the last 4 digits of your WCU ID (1133) number (1 digit per clock cycle). Complete each of the steps which follow.

(a) Draw the state diagram for this machine.
(b) Write RTL Verilog code which implements this design. Submit your printed source code by the due date and time.
(c) Create a test bench to exercise the design through all of its states and functions. Submit your test bench source code and a simulation waveform. The simulation waveform must show the digits of your WCU ID and no one else's.

In: Electrical Engineering

1. How many complex numbers z are there such that z3 = 1? 2. Translate x(t)...

1. How many complex numbers z are there such that z3 = 1?

2. Translate x(t) = -cos(πt + π/3) into standard form A⋅sin(2πft + φ) (There are multiple correct answers)

3. If fs = 100 Hz, what are three aliasing frequencies for f = 80 Hz?

4. A signal x is delayed by one sample and scaled by −1/2, producing a new signal y[n] = −1 2 x[n − 1]. (a) How does Y[m] relate to X[m]? (b) What about |Y[m]| and |X[m]|?

5. If a signal x’s DFT has entirely real coefficients X[m] (has no imaginary component), what can you deduce about x? Consider the phase for each analysis frequency.

6. Let x[n] be a signal with N = 5000 samples. (a) If you compute an STFT with a frame length of K = 1000 and hop length h = 250, what will be the shape of the resulting spectrogram? (b) How would it change if you set K = 2000? (c) What if you set h = 100?

In: Electrical Engineering

gow does scan expansion mesh and scan expansion meshless work in a oscilliscope? in other words...

gow does scan expansion mesh and scan expansion meshless work in a oscilliscope?
in other words what happens inside an oscilliscope when i turn the time/div knob?

In: Electrical Engineering

PN Junctions and breakdown 1. Draw and interpret energy band diagram for pn junction in equilibrium,...

PN Junctions and breakdown

1. Draw and interpret energy band diagram for pn junction in equilibrium, forward, and reverse bias

2. Describe what physically happens (And why) when you put n-Si in contact with p-Si (e.g., junction formation)

3. Calculate Vo, W, Wn, Wp

4. Describe how/why current flows in forward and reverse bias.

5. Utilize law of junction to calculate the minority carrier concentration just outside the depletion layer

6. Quantify the forward and reverse bias current in a p-n junction given appropriate information

7. Describe the meaning of the diode ideality factor for values of 1 and 2 and in between

8. Describe what constitutes “short diode” conditions

9. Calculate the depletion layer capacitance given sufficient information

10. Identify the two mechanisms that allow for reverse bias breakdown of a diode.

11. Describe what occurs during Zener tunneling and avalanche and the conditions that this will occur

In: Electrical Engineering

This concept of  (A/D conversion and sampling rates) could be relevant to envisioned future career field. Could...

This concept of  (A/D conversion and sampling rates) could be relevant to envisioned future career field.

Could you write a paragraph commenting please?

In: Electrical Engineering

module traffic(clk, reset, P1, P2, P3, P4, PL); input clk; input reset; output[4:0] P1; output[4:0] P2;...

module traffic(clk, reset, P1, P2, P3, P4, PL);
input clk;
input reset;
output[4:0] P1;
output[4:0] P2;
output[4:0] P3; // four roads
output [4:0] P4;
output[3:0] PL; //Pl is pedestrian

reg [4:0] P1;
reg [4:0] P2;
reg [4:0] P3;
reg [4:0] P4;
reg [3:0] PL;
reg [4:0] sig;

always @(posedge clk or negedge reset)
begin
   if(reset == 1'b0)begin
       P1 <= 5'b00100;
       P2 <= 5'b00100;
       P3 <= 5'b00100;
       P4 <= 5'b00100;
       PL <= 4'b1111;
       sig <= 5'b00000;
   end
   else begin
       sig <= sig + 1;
      
       case(sig[4:0])
       5'b00000:begin
       P1 <= 5'b10011; //path 1 is greeen
       P2 <= 5'b00100; //all other paths are red
       P3 <= 5'b10011;
       P4 <= 5'b10011;
       PL <= 4'b1111;
       end
      
       5'b00100:begin
       P1 <= 5'b01000; //path 1 is yellow
       P2 <= 5'b00100; // all other paths are red
       P3 <= 5'b00100;
       P4 <= 5'b00100;
       PL <= 4'b1111;
       end

       5'b01000:begin
       P1 <= 5'b00100; //path 1 is red
       P2 <= 5'b10011; //path 2 is green
       P3 <= 5'b00100; // all other paths are red
       P4 <= 5'b00100;
       PL <= 4'b1111;
       end

       5'b01100:begin
       P1 <= 5'b00100;
       P2 <= 5'b01000; //path 2 is yellow
       P3 <= 5'b00100; // all other paths are red
       P4 <= 5'b00100;
       PL <= 4'b1111;
       end

       5'b10000:begin
       P1 <= 5'b00100;
       P2 <= 5'b00100; //path 3 is green
       P3 <= 5'b10011; // all other paths are red
       P4 <= 5'b00100;
       PL <= 4'b1111;
       end

       5'b10100:begin
       P1 <= 5'b00100;
       P2 <= 5'b00100; //path 3 is yellow
       P3 <= 5'b01000; // all other paths are red
       P4 <= 5'b00100;
       PL <= 4'b1111;
       end

       5'b11000:begin
       P1 <= 5'b00100;
       P2 <= 5'b00100; //all other paths are red
       P3 <= 5'b00100; // path 4 is yello
       P4 <= 5'b10011;
       PL <= 4'b1111;
       end

       5'b11100:begin
       P1 <= 5'b00100; //all other paths are red
       P2 <= 5'b00100;
       P3 <= 5'b00100;
       P4 <= 5'b00100;
       PL <= 4'b0000; //pedestrian green
       end

       5'b11111:sig<= 6'b00000;

       default:begin     
      
       end
   endcase

   end
end

endmodule

can anyone write a testbench for this code in Verilog.

In: Electrical Engineering

Explain Peterson coil.

Explain Peterson coil.

In: Electrical Engineering

? A. B. C. D. E. 1.The amount of charge on a capacitor in an electric...

? A. B. C. D. E. 1.The amount of charge on a capacitor in an electric circuit decreases by 30% each second.

   ?    A    B    C    D    E      2. Polluted water is passed through a series of filters. Each filter removes all but 30% of the remaining impurities from the water.

   ?    A    B    C    D    E      3. In 1950, the population of a town was 3000 people. Over the course of the next 50 years, the town grew at a rate of 10% per decade.

   ?    A    B    C    D    E      4. The percent of a lake's surface covered by algae, initially at 35%, was halved each year since the passage of anti-pollution laws.

   ?    A    B    C    D    E      5. In 1950, the population of a town was 3000 people. Over the course of the next 50 years, the town grew at a rate of 250 people per year.


A. ?(?)=?(0.3)?f(x)=B(0.3)x

B. ?(?)=?(2)−?f(x)=A(2)−x

C. ?(?)=?0+??f(x)=P0+rx

D. ?(?)=?(0.7)?f(x)=B(0.7)x

E. ?(?)=?0(1+?)?f(x)=P0(1+r)x

In: Electrical Engineering

In MATLAB, the script should use both for and while loops. Game Mode: Randomly generates 10...

In MATLAB, the script should use both for and while loops.

Game Mode: Randomly generates 10 unique (e.g. non-repeating) multiplication problems that involve multiplying the integer selected in the previous step by an integer value between 2 and 12, inclusive, after which the following report should be displayed in the Command Window.

You correctly answered __ out of __ problems (__%) involving __s.

The number of correctly answered problems appears in the first blank, the total number of problems appears in the second blank, the percentages of problems answered correctly appears in the third blank, and the integer the user selected in step 1 appears in the last blank.

-- After completing a round of the game, the user should have the option to play another round or quit the game.

In: Electrical Engineering

Write a note on UNSW G17 substation.

Write a note on UNSW G17 substation.

In: Electrical Engineering

What is the main difference between gated and edge triggered digital devices?

What is the main difference between gated and edge triggered digital devices?

In: Electrical Engineering

Design a high-passfilter that reduces magnitudeof H(jw) to0.4forthe signal with 1000(Y+1) Hz.a)Use 10 Ωresistorand calculate the...

Design a high-passfilter that reduces magnitudeof H(jw) to0.4forthe signal with 1000(Y+1) Hz.a)Use 10 Ωresistorand calculate the value of the inductanceof the filter. Calculate the cutoff frequencyof the filter.b)Design another filter for the same purpose by using the same resistorcombined with a capacitor. Find the value of the capacitance. Findthemagnitudes of H(jw) for 200Hzand20000Hz frequenciesand sketchthe frequency responsegraph of the filter.c)(20+X)Ωresistive load is connected across the output terminals of the firstfilter. Find the new cutoff frequency (in hertz) of the loaded filter. Explain the effect of connecting load by considering the new cutoff frequency. Derive an expression for the new transfer function for the loaded case.
x=2, y=2, z=8 (asap pls)

In: Electrical Engineering

Mention the administrative solutions required in a HV lab environment

Mention the administrative solutions required in a HV lab environment

In: Electrical Engineering

What is the difference in the voltage output of a BJT Transistor switch circuit    and...

What is the difference in the voltage output of a BJT Transistor switch circuit    and a BJT Emitter follower circuit?

In: Electrical Engineering