Question

In: Electrical Engineering

write gate level 16bit carry look ahead adder in verilog without any assign and always in...

write gate level 16bit carry look ahead adder in verilog without any assign and always in the code.

Solutions

Expert Solution

module cla(input [15:0]a,b,input cin,output [15:0]s,output c15
);

wire p0,p1,p2,p3,p4,p5,p6,p7,p8,p9,p10,p11,p12,p13,p14,p15,
c0,c1,c2,c3,c4,c5,c6,c7,c8,c9,c10,c11,c12,c13,c14, g0,g1,g2,g3,g4,g5,g6,g7,g8,g9,g10,g11,g12,g13,g14,g15;

wire i0,i1,i2,i3,i4,i5,i6,i7,i8,i9,i10,i11,i12,i13,i14,i15,i16,i17,i18,i19,i20,i21,i22,i23,i24,i25,

i26,i27,i28,i29,i30,i31,i32,i33,i34,i35,i36,i37,i38,i39
,i40,i41,i42,i43,i44,i45,i46,i47,i48,i49
,i50,i51,i52,i53,i54,i55,i56,i57,i58,i59
,i60,i61,i62,i63,i64,i65,i66,i67,i68,i69
,i70,i71,i72,i73,i74,i75,i76,i77,i78,i79
,i80,i81,i82,i83,i84,i85,i86,i87,i88,i89;

wire j0,j1,j2,j3,j4,j5,j6,j7,j8,j9,j10,j11,j12,j13;
wire k0,k1,k2,k3,k4,k5,k6,k7,k8,k9,k10,k11,k12,k13,k14;
wire l0,l1,l2,l3,l4,l5,l6,l7,l8,l9,l10,l11,l12,l13,l14,l15;

//propagate calculation
xor(p0,a[0],b[0]);
xor(p1,a[1],b[1]);
xor(p2,a[2],b[2]);
xor(p3,a[3],b[3]);
xor(p4,a[4],b[4]);
xor(p5,a[5],b[5]);
xor(p6,a[6],b[6]);
xor(p7,a[7],b[7]);
xor(p8,a[8],b[8]);
xor(p9,a[9],b[9]);
xor(p10,a[10],b[10]);
xor(p11,a[11],b[11]);
xor(p12,a[12],b[12]);
xor(p13,a[13],b[13]);
xor(p14,a[14],b[14]);
xor(p15,a[15],b[15]);

//generate calculation

and(g0,a[0],b[0]);
and(g1,a[1],b[1]);
and(g2,a[2],b[2]);
and(g3,a[3],b[3]);
and(g4,a[4],b[4]);
and(g5,a[5],b[5]);
and(g6,a[6],b[6]);
and(g7,a[7],b[7]);
and(g8,a[8],b[8]);
and(g9,a[9],b[9]);
and(g10,a[10],b[10]);
and(g11,a[11],b[11]);
and(g12,a[12],b[12]);
and(g13,a[13],b[13]);
and(g14,a[14],b[14]);
and(g15,a[15],b[15]);

//carrys calculation

and(i0,p0,cin);
or(c0,i0,g0);

and(i1,p1,p0,cin);
and(i2,p1,g0);
or(c1,i1,i2,g1);

and(i3,p2,p1,p0,cin);
and(i4,p2,p1,g0);
and(i5,p2,g1);
or(c2,i3,i4,i5,g2);

and(i6,p3,p2,p1,p0,cin);
and(i7,p3,p2,p1,g0);
and(i8,p3,p2,g1);
and(i9,p3,g2);
or(c3,i6,i7,i8,i9,g3);

and(i10,p4,p3,p2,p1,p0,cin);
and(i11,p4,p3,p2,p1,g0);
and(i12,p4,p3,p2,g1);
and(i13,p4,p3,g2);
and(i14,p4,g3);
or(c4,i10,i11,i12,i13,i14,g4);

and(i15,p5,p4,p3,p2,p1,p0,cin);
and(i16,p5,p4,p3,p2,p1,g0);
and(i17,p4,p3,p2,p5,g1);
and(i18,p4,p3,p5,g2);
and(i19,p4,p5,g3);
and(i20,p5,g4);
or(c5,i15,i16,i17,i18,i19,i20,g5);
and(i21,p6,p5,p4,p3,p2,p1,p0,cin);
and(i22,p5,p4,p3,p2,p1,p6,g0);
and(i23,p5,p4,p3,p2,p6,g1);
and(i24,p4,p3,p6,p5,g2);
and(i25,p4,p6,p5,g3);
and(i26,p6,p5,g4);
and(i27,p6,g5);
or(c6,i21,i22,i23,i24,i25,i26,i27,g6);

and(i28,p6,p7,p5,p4,p3,p2,p1,p0,cin);
and(i29,p6,p5,p4,p3,p2,p1,p7,g0);
and(i30,p5,p4,p3,p2,p7,p6,g1);
and(i31,p5,p4,p3,p7,p6,g2);
and(i32,p4,p7,p6,p5,g3);
and(i33,p7,p6,p5,g4);
and(i34,p6,p7,g5);
and(i35,p7,g6);
or(c7,i28,i29,i30,i31,i32,i33,i34,i35,g7);

and(i36,p8,p6,p7,p5,p4,p3,p2,p1,p0,cin);
and(i37,p6,p7,p5,p4,p3,p2,p1,p8,g0);
and(i38,p6,p5,p4,p3,p2,p8,p7,g1);
and(i39,p5,p4,p3,p8,p7,p6,g2);
and(i40,p5,p4,p8,p7,p6,g3);
and(i41,p8,p7,p6,p5,g4);
and(i42,p7,p6,p8,g5);
and(i43,p8,p7,g6);
and(i44,p8,g7);
or(c8,i36,i37,i38,i39,i40,i41,i42,i43,i44,g8);

and(i45,p9,p8,p6,p7,p5,p4,p3,p2,p1,p0,cin);
and(i46,p8,p6,p7,p5,p4,p3,p2,p1,p9,g0);
and(i47,p6,p7,p5,p4,p3,p2,p9,p8,g1);
and(i48,p6,p5,p4,p3,p9,p8,p7,g2);
and(i49,p5,p4,p9,p8,p7,p6,g3);
and(i50,p5,p9,p8,p7,p6,g4);
and(i51,p8,p7,p6,p9,g5);
and(i52,p7,p9,p8,g6);
and(i53,p8,p9,g7);
and(i54,p9,g8);
or(c9,i45,i46,i47,i48,i49,i50,i51,i52,i53,i54,g9);

and(i55,p10,p9,p8,p6,p7,p5,p4,p3,p2,p1,p0,cin);
and(i56,p9,p8,p6,p7,p5,p4,p3,p2,p1,p9,g0);
and(i57,p8,p6,p7,p5,p4,p3,p2,p10,p9,g1);
and(i58,p6,p7,p5,p4,p3,p10,p9,p8,g2);
and(i59,p6,p5,p4,p10,p9,p8,p7,g3);
and(i60,p5,p10,p9,p8,p7,p6,g4);
and(i61,p10,p9,p8,p7,p6,g5);
and(i62,p8,p7,p10,p9,g6);
and(i63,p10,p9,p8,g7);
and(i64,p10,p9,g8);
and(i65,p10,g9);
or(c10,i55,i56,i57,i58,i59,i60,i61,i62,i63,i64,i65,g10);

and(i65,p11,p10,p9,p8,p6,p7,p5,p4,p3,p2,p1,p0,cin);
and(i66,p10,p9,p8,p6,p7,p5,p4,p3,p2,p1,p11,g0);
and(i67,p9,p8,p6,p7,p5,p4,p3,p2,p11,p9,g1);
and(i68,p8,p6,p7,p5,p4,p3,p11,p10,p9,g2);
and(i69,p6,p7,p5,p4,p11,p10,p9,p8,g3);
and(i70,p6,p5,p11,p10,p9,p8,p7,g4);
and(i71,p11,p10,p9,p8,p7,p6,g5);
and(i72,p10,p9,p8,p7,p11,g6);
and(i73,p8,p11,p10,p9,g7);
and(i74,p10,p9,p11,g8);
and(i75,p10,p11,g9);
and(i76,p11,g10);
or(c11,i65,i66,i67,i68,i69,i70,i71,i72,i73,i74,i75,i76,g11);

and(i77,p12,p11,p10,p9,p8,p6,p7,p5,p4,p3,p2,p1,p0,cin);
and(i78,p11,p10,p9,p8,p6,p7,p5,p4,p3,p2,p1,p12,g0);
and(i79,p10,p9,p8,p6,p7,p5,p4,p3,p2,p12,p11,g1);
and(i80,p9,p8,p6,p7,p5,p4,p3,p12,p11,p9,g2);
and(i81,p8,p6,p7,p5,p4,p12,p11,p10,p9,g3);
and(i82,p6,p7,p5,p12,p11,p10,p9,p8,g4);
and(i83,p6,p12,p11,p10,p9,p8,p7,g5);
and(i84,p11,p10,p9,p8,p7,p12,g6);
and(i85,p10,p9,p8,p12,p11,g7);
and(i86,p12,p11,p10,p9,g8);
and(i87,p10,p12,p11,g9);
and(i88,p12,p11,g10);
and(i89,p12,g11);
or(c12,i77,i78,i79,i80,i81,i82,i83,i84,i85,i86,i87,i88,i89,g12);

and(j0,p12,p11,p10,p9,p8,p6,p7,p5,p4,p3,p2,p1,p0,cin);
and(j1,p12,p11,p10,p9,p8,p6,p7,p5,p4,p3,p2,p1,p13,g0);
and(j2,p11,p10,p9,p8,p6,p7,p5,p4,p3,p2,p13,p12,g1);
and(j3,p10,p9,p8,p6,p7,p5,p4,p3,p13,p12,p11,g2);
and(j4,p9,p8,p6,p7,p5,p4,p13,p12,p11,p9,g3);
and(j5,p8,p6,p7,p5,p13,p12,p11,p10,p9,g4);
and(j6,p6,p7,p13,p12,p11,p10,p9,p8,g5);
and(j7,p13,p12,p11,p10,p9,p8,p7,g6);
and(j8,p11,p10,p9,p8,p13,p12,g7);
and(j9,p10,p9,p13,p12,p11,g8);
and(j10,p12,p11,p10,p13,g9);
and(j11,p13,p12,p11,g10);
and(j12,p12,p13,g11);
and(j13,p13,g12);
or(c13,j0,j1,j2,j3,j4,j5,j6,j7,j8,j9,j10,j11,j12,j13,g13);

and(k14,p12,p11,p10,p9,p8,p6,p7,p5,p4,p3,p2,p1,p0,cin);
and(k0,p12,p11,p10,p9,p8,p6,p7,p5,p4,p3,p2,p1,p14,g0);
and(k1,p12,p11,p10,p9,p8,p6,p7,p5,p4,p3,p2,p14,p13,g1);
and(k2,p11,p10,p9,p8,p6,p7,p5,p4,p3,p14,p13,p12,g2);
and(k3,p10,p9,p8,p6,p7,p5,p4,p14,p13,p12,p11,g3);
and(k4,p9,p8,p6,p7,p5,p14,p13,p12,p11,p9,g4);
and(k5,p8,p6,p7,p14,p13,p12,p11,p10,p9,g5);
and(k6,p14,p7,p13,p12,p11,p10,p9,p8,g6);
and(k7,p13,p12,p11,p10,p9,p8,p14,g7);
and(k8,p11,p10,p9,p14,p13,p12,g8);
and(k9,p10,p14,p13,p12,p11,g9);
and(k10,p12,p11,p14,p13,g10);
and(k11,p13,p12,p14,g11);
and(k12,p14,p13,g12);
and(k13,p14,g13);
or(c14,k0,k1,k2,k3,k4,k5,k6,k7,k8,k9,k10,k11,k12,k13,k14,g14);

and(l15,p12,p11,p10,p9,p8,p6,p7,p5,p4,p3,p2,p1,p0,cin);
and(l14,p12,p11,p10,p9,p8,p6,p7,p5,p4,p3,p2,p1,p15,g0);
and(l0,p12,p11,p10,p9,p8,p6,p7,p5,p4,p3,p2,p15,p14,g1);
and(l1,p12,p11,p10,p9,p8,p6,p7,p5,p4,p3,p15,p14,p13,g2);
and(l2,p11,p10,p9,p8,p6,p7,p5,p4,p15,p14,p13,p12,g3);
and(l3,p10,p9,p8,p6,p7,p5,p15,p14,p13,p12,p11,g4);
and(l4,p9,p8,p6,p7,p15,p14,p13,p12,p11,p9,g5);
and(l5,p8,p15,p7,p14,p13,p12,p11,p10,p9,g6);
and(l6,p14,p15,p13,p12,p11,p10,p9,p8,g7);
and(l7,p13,p12,p11,p10,p9,p15,p14,g8);
and(l8,p11,p10,p15,p14,p13,p12,g9);
and(l9,p15,p14,p13,p12,p11,g10);
and(l10,p12,p15,p14,p13,g11);
and(l11,p13,p15,p14,g12);
and(l12,p14,p15,g13);
and(l13,p15,g14);
or(c15,l0,l1,l2,l3,l4,l5,l6,l7,l8,l9,l10,l11,l12,l13,l14,l15,g14);

//sum calculation


xor(s[0],a[0],b[0],cin);
xor(s[1],a[1],b[1],c0);
xor(s[2],a[2],b[2],c1);
xor(s[3],a[3],b[3],c2);
xor(s[4],a[4],b[4],c3);
xor(s[5],a[5],b[5],c4);
xor(s[6],a[6],b[6],c5);
xor(s[7],a[7],b[7],c6);
xor(s[8],a[8],b[8],c7);
xor(s[9],a[9],b[9],c8);
xor(s[10],a[10],b[10],c9);
xor(s[11],a[11],b[11],c10);
xor(s[12],a[12],b[12],c11);
xor(s[13],a[13],b[13],c12);
xor(s[14],a[14],b[14],c13);
xor(s[15],a[15],b[15],c14);

endmodule


Related Solutions

write gate level 4bit carry look ahead adder in verilog without any assign and always in...
write gate level 4bit carry look ahead adder in verilog without any assign and always in the code.
SYSTEM VERILOG: Using your preferred HDL program, design a complete 4-bit Carry Look Ahead (CLA) adder...
SYSTEM VERILOG: Using your preferred HDL program, design a complete 4-bit Carry Look Ahead (CLA) adder module.
Problem 3.73 (1-bit full adder using carry lookahead – gate level circuit) 3.73 Design a 4-bit...
Problem 3.73 (1-bit full adder using carry lookahead – gate level circuit) 3.73 Design a 4-bit full adder using carry look-ahead rather than ripple carry.
Digital System Design Write the verilog HDL code for 2-4 decoder (Gate level modeling) along with...
Digital System Design Write the verilog HDL code for 2-4 decoder (Gate level modeling) along with the testbench and simulate using ModelSim. Upload the assignment (i) code (ii) testbench (iii) simulation in single pdf file.
Write a verilog code for 5 to 8 multiplier using fourbit adder
Write a verilog code for 5 to 8 multiplier using fourbit adder
Implement a 4x4 multiplier using gate level (verilog code and test bench)
Implement a 4x4 multiplier using gate level (verilog code and test bench)
Write down the VERILOG code for an XOR gate and the testbench code to test it
Write down the VERILOG code for an XOR gate and the testbench code to test it
Design a 4-bit multiplier by using 4 bit full adder and write a verilog code.
Design a 4-bit multiplier by using 4 bit full adder and write a verilog code.
Provide the VHDL specification of a hybrid 32-bit adder that cascades 2 12 bit carry look...
Provide the VHDL specification of a hybrid 32-bit adder that cascades 2 12 bit carry look ahead adders and one 10 bit carry look ahead adder. a) Compare your adder with a full 32-bit carry-look ahead in performance and cost. b) Compare your adder with a full combinational adder in performance and cost c) Compare your adder with a ripple-carry adder in performance and cost. d) Compare your adder to a bit serial (sequential) adder in performance and cost. e)...
Question B Write an 8 bit adder module in System Verilog by appropriately connecting two 4...
Question B Write an 8 bit adder module in System Verilog by appropriately connecting two 4 bit adders (the System Verilog code of a 4 bit adder is available in the lecture notes). Instantiate your 8 bit adder module on DE2 board. Design a test circuit on DE2 board that allows us to test the 8 bit adder using the switches and the seven segment displays on DE2 board. The test circuit will need the module you designed for Part...
ADVERTISEMENT
ADVERTISEMENT
ADVERTISEMENT