Question

write gate level 4bit carry look ahead adder in verilog without any assign and always in the code.

Answer 1

the gate level module is shown below:

// Code your design here
module full_adder (a,b,cin,s,cout);
input a,b,cin;
output cout,s;
wire w1,w2,w3,w4,w5;
xor x1(w1,a,b);
xor x2(s,w1,cin);
and a1(w2,a,b);
and a2(w3,b,cin);
and a3(w4,a,cin);
or r1(w5,w2,w3);
or r2(cout,w5,w4);
endmodule
module carry_lookahead_adder_4_bit
(
input [3:0] i_add1,
input [3:0] i_add2,
output [4:0] o_result
);

wire [4:0] w_C;
wire [3:0] w_G, w_P, w_SUM;
wire [3:0] w;

full_adder full_adder_bit_0
(
.a(i_add1[0]),
.b(i_add2[0]),
.cin(w_C[0]),
.s(w_SUM[0]),
.cout()
);

full_adder full_adder_bit_1
(
.a(i_add1[1]),
.b(i_add2[1]),
.cin(w_C[1]),
.s(w_SUM[1]),
.cout()
);

full_adder full_adder_bit_2
(
.a(i_add1[2]),
.b(i_add2[2]),
.cin(w_C[2]),
.s(w_SUM[2]),
.cout()
);

full_adder full_adder_bit_3
(
.a(i_add1[3]),
.b(i_add2[3]),
.cin(w_C[3]),
.s(w_SUM[3]),
.cout()
);

// Create the Generate (G) Terms: Gi=Ai*Bi
and an1(w_G[0],i_add1[0],i_add2[0]);
and an2(w_G[1],i_add1[1],i_add2[1]);
and an3(w_G[2],i_add1[2],i_add2[2]);
and an4(w_G[3],i_add1[3],i_add2[3]);

// Create the Propagate Terms: Pi=Ai+Bi
or or1(w_P[0],i_add1[0],i_add2[0]);
or or2(w_P[1],i_add1[1],i_add2[1]);
or or3(w_P[2],i_add1[2],i_add2[2]);
or or4(w_P[3],i_add1[3],i_add2[3]);

// Create the Carry Terms:
buf b1(w_C[0],1'b0); // no carry input
and c1(w[0],w_P[0],w_C[0]);
or oc1 (w_C[1],w_G[0],w[0]);
and c2(w[1],w_P[1],w_C[1]);
or oc2(w_C[2],w_G[1],w[1]);
and c3(w[2],w_P[2],w_C[2]);
or oc3(w_C[3],w_G[2],w[2]);
and c4(w[3],w_P[3],w_C[3]);
or oc4 (w_C[4],w_G[3],w[3]);

// result concatination
buf res1(o_result[4],w_C[4]);
buf res2(o_result[3],w_SUM[3]);
buf res3(o_result[2],w_SUM[2]);
buf res4(o_result[1],w_SUM[1]);
buf res5(o_result[0],w_SUM[0]);

endmodule

testbench:

// Code your testbench here
// or browse Examples
module test();
reg [3:0] i_add1,i_add2;
wire [4:0] o_result;
carry_lookahead_adder_4_bit ccc1(.*);
initial
begin
i_add1=5;i_add2=6;
#2 i_add1=15;i_add2=1;
end
initial
$monitor("%b %b %b",i_add1,i_add2,o_result);
endmodule

output:

0101 0110 01011
1111 0001 10000