Question

Write the code to compare two 8-bit buses, a and b. The output signal is agrb for “a greater than b.”

Answer 1

-----------the VHDL code for your design is--------------

---------VHDL CODE-------------
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_UNSIGNED.all;
entity compare_8bit is
     port(
         a : in STD_LOGIC_VECTOR(7 downto 0);
         b : in STD_LOGIC_VECTOR(7 downto 0);
       
         agrb : out STD_LOGIC
       
         );
end compare_8bit;

architecture Behavioural of compare_8bit is
begin

agrb<= '1' when (a>b) else
               '0';

end Behavioural;

////////the verilog module for your design is ////////////////

module compare_8_bit (a,b,agrb);///declare the inputs and output
input [7:0] a,b;
output agrb;    ///output signal Q (Q3Q2Q1Q0)



assign agrb=(a>b)?1:0;///?-is ternaery operator compares a,b
                        //ifa>b then agrb signal equal to 1 otherwise 0
endmodule

(If you satisfied rate the answer, If you have any query leave a comment, Thank you)