Question

Implement a 2 by 2 multiplier using structure VHDL. The circuit will have two 2-bit unsigned inputs (A and B), a 4-bit unsigned product outputs (P). you must use some full adders and gates (AND, OR, NOT, XOR).

Answer 1

---------VHDL code for unsigned multiplier-----------

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity Unsinmul is
Port ( A,B : in STD_LOGIC_VECTOR(1 DOWNTO 0);

S : out STD_LOGIC_VECTOR(3 DOWNTO 0));
end Unsinmul;
architecture structural of Unsinmul is

component fulladder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end component;

component andtop is
    Port ( INA1, INA2 : in STD_LOGIC;
           OA   : out STD_LOGIC);
end component;

signal k1,k2,k3,k4:STD_LOGIC;
begin
u1:andtop port map(A(0),B(0),S(0));
u2:andtop port map(A(1),B(0),k1);
u3:andtop port map(A(0),B(1),k2);
u4:andtop port map(A(1),B(1),k3);
u5:fulladder port map('0',k1,k2,S(1),k4);
u6:fulladder port map(k4,k3,'0',S(2),S(3));

end structural;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity fulladder is
Port ( A : in STD_LOGIC;
B : in STD_LOGIC;
Cin : in STD_LOGIC;
S : out STD_LOGIC;
Cout : out STD_LOGIC);
end fulladder;

architecture dataflow of fulladder is

begin

S <= A XOR B XOR Cin ;
Cout <= (A AND B) OR (Cin AND A) OR (Cin AND B) ;

end dataflow;

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity andtop is
    Port ( INA1, INA2 : in STD_LOGIC;
           OA   : out STD_LOGIC);
end andtop;

architecture Behavioral of andtop is
begin
    OA <= INA1 and INA2;
end Behavioral;

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