Question

a) Implement a decade counter using FF JK-MS.
b) Implement a counter dividing by 6 using FF JK-MS.

c) Repeat the previous exercises using FF Type-D.

Answer 1

We saw previously that toggle T-type flip flops can be used as individual divide-by-two counters. If we connect together several toggle flip-flops in a series chain we can produce a digital counter which stores or display the number of times a particular count sequence has occurred.

Clocked T-type flip-flops act as a binary divide-by-two counter and in asynchronous counters, the output of one counting stage provides the clock pulse for the next stage. Then a flip-flop counter has two possible output states and by adding more flip-flop stages, we can make a divide-by-2N counter. But the problem with 4-bit binary counters is that they count from 0000 to 1111. That is from 0 to 15 in decimal.

To make a digital counter which counts from 1 to 10, we need to have the counter count only the binary numbers 0000 to 1001. That is from 0 to 9 in decimal and fortunately for us, counting circuits are readily available as integrated circuits with one such circuit being the Asynchronous 74LS90 Decade Counter.

Digital counters count upwards from zero to some pre-determined count value on the application of a clock signal. Once the count value is reached, resetting them returns the counter back to zero to start again.

A decade counter counts in a sequence of ten and then returns back to zero after the count of nine. Obviously to count up to a binary value of nine, the counter must have at least four flip-flops within its chain to represent each decimal digit as shown.

BCD Counter State Diagram

Then a decade counter has four flip-flops and 16 potential states, of which only 10 are used and if we connected a series of counters together we could count to 100 or 1,000 or to whatever final count number we choose.

The total number of counts that a counter can count too is called its MODULUS. A counter that returns to zero after n counts is called a modulo-n counter, for example a modulo-8 (MOD-8), or modulo-16 (MOD-16) counter, etc, and for an “n-bit counter”, the full range of the count is from 0 to 2n-1.

But as we saw in the Asynchronous Counters tutorial, that a counter which resets after ten counts with a divide-by-10 count sequence from binary 0000(decimal “0”) through to 1001 (decimal “9”) is called a “binary-coded-decimal counter” or BCD Counter for short and a MOD-10 counter can be constructed using a minimum of four toggle flip-flops.

It is called a BCD counter because its ten state sequence is that of a BCD code and does not have a regular pattern, unlike a straight binary counter. Then a single stage BCD counter such as the 74LS90 counts from decimal 0 to decimal 9 and is therefore capable of counting up to a maximum of nine pulses. Note also that a digital counter may count up or count down or count up and down (bidirectional) depending on an input control signal.

Binary-coded-decimal code is an 8421 code consisting of four binary digits. The 8421 designation refers to the binary weight of the four digits or bits used. For example, 23 = 8, 22 = 4, 21 = 2 and 20 = 1. The main advantage of BCD code is that it allows for the easy conversion between decimal and binary forms of numbers.

The 74LS90 BCD Counter

The 74LS90 integrated circuit is basically a MOD-10 decade counter that produces a BCD output code. The 74LS90 consists of four master-slave JK flip-flops internally connected to provide a MOD-2 (count-to-2) counter and a MOD-5 (count-to-5) counter. The 74LS90 has one independent toggle JK flip-flop driven by the CLK A input and three toggle JK flip-flops that form an asynchronous counter driven by the CLK B input as shown.

74LS90 BCD Counter

The counters four outputs are designated by the letter symbol Q with a numeric subscript equal to the binary weight of the corresponding bit in the BCD counter circuits code. So for example, QA, QB, QCand QD. The 74LS90 counting sequence is triggered on the negative going edge of the clock signal, that is when the clock signal CLK goes from logic 1 (HIGH) to logic 0 (LOW).

The additional input pins R1 and R2 are counter “reset” pins while inputs S1 and S2 are “set” pins. When connected to logic 1, the Reset inputs R1 and R2 reset the counter back to zero, 0 (0000), and when the Set inputs S1 and S2 are connected to logic 1, they Set the counter to maximum, or 9 (1001) regardless of the actual count number or position.

As we said before, the 74LS90 counter consists of a divide-by-2 counter and a divide-by-5 counter within the same package. Then we can use either counter to produce a divide-by-2 frequency counter only, a divide-by-5 frequency counter only or the two together to produce our desired divide-by-10 BCD counter.

With the four flip-flops making up the divide-by-5 counter section disabled, if a clock signal is applied to input pin 14 (CLKA) and the output taken from pin 12 (QA), we can produce a standard divide-by-2 binary counter for use in frequency dividing circuits as shown.

74LS90 Divide-by-2 Counter

To produce a standard divide-by-5 counter, we can disable the first flip-flop above, and apply the clock input signal directly to pin 1 (CLKB) with the output signal being taken from pin 11 (QD) as shown

74LS90 Divide-by-5 Counter

Note that with this divide-by-5 counter configuration, the output waveform is not symmetrical but has a 4:1 mark-space ratio. That is four input clock signals creates a LOW or logic “0” output and the fifth input clock signal produces a HIGH or logic “1” output.

To produce a divide-by-10 BCD decade counter, both internal counter circuits are used giving a 2 times 5 divide-by value. Since the first output QA from flip-flop “A” is not internally connected to the succeeding stages, the counter can be extended to form a 4-bit BCD counter by connecting this QA output to the CLKB input as shown.