Question

1. Create a 4-bit Register
2. 1. This is very similar to your flip-flop design from lab task 1. Ensure that your 4-bit register has inputs “D” (dat, “CLK” (the clock), and “RST” (an asynchronous reset), and an output “Q”.
3. 2. [3 pts] Create a test bench and ensure that your 4-bit register operates correctly (test your reset signal and ensure that you can store a couple different values in the register). If your output behavior is correct, then copy your VHDL design code and simulation screenshot below:
4. 1. Place your 4-bit register’s VHDL design module code here (copy-paste as text, not an image):
5. 2. Place a screenshot of your simulation here (enlarge your waveform and do not crop the image (it should show the whole screen) or you will lose points):
6. 3. Explain why your circuit is (or is not) working correctly:

Answer 1

-- VHDL CODE

-- Code your design here
library IEEE;
use IEEE.std_logic_1164.all;

entity register_4bit is
port ( CLK: in std_logic;
D : in std_logic ;
RST : in std_logic;
Q : out std_logic
);
end register_4bit;

architecture structural of register_4bit is

--d flipflop componenet declartion

component dff is
port ( CLK: in std_logic;
D : in std_logic;
RST : in std_logic;
Q : out std_logic );
end component;

signal Q_reg : std_logic_vector(3 downto 0) ;

begin

--instantiate D fliplfops
U1: dff port map ( CLK,D,RST,Q_reg(3));
U2: dff port map ( CLK,Q_reg(3),RST,Q_reg(2));
U3: dff port map ( CLK,Q_reg(2),RST,Q_reg(1));
U4: dff port map ( CLK,Q_reg(1),RST,Q_reg(0));

Q<= Q_reg(0);

end structural;

-- d flilfop verilog code
library IEEE;
use IEEE.std_logic_1164.all;
entity dff is
port ( CLK: in std_logic;
D : in std_logic;
RST : in std_logic;
Q : out std_logic );
end dff;

architecture rtl of dff is

begin
process(CLK,RST)
begin
if (RST) then
Q<='0';
elsif (rising_edge(CLK)) then
Q<=D;
end if;
end process;
end rtl;

-- Code your testbench here
library IEEE;
use IEEE.std_logic_1164.all;

entity test is
end test;

architecture behavioral of test is

component register_4bit is
port ( CLK: in std_logic;
D : in std_logic ;
RST : in std_logic;
Q : out std_logic
);
end component;

signal CLK,D,RST: std_logic;
signal Q : std_logic;

begin
--innstantiate DUT
DUT: register_4bit port map ( CLK => CLK , D => D , RST => RST , Q => Q );

--clocl generation
process
begin
CLK <= '0';
wait for 10 ns;
CLK <= '1';
wait for 10 ns;
end process;

--input stimulus
process
begin
RST <= '1'; D <= '0';
wait for 10 ns;
RST <= '0'; D <= '1';
wait for 10 ns;
RST <= '0'; D <= '0';
wait for 10 ns;
RST <= '0'; D <= '1';
wait for 10 ns;
RST <= '0'; D <= '1';
wait for 10 ns;
RST <= '0'; D <= '0';
wait for 10 ns;
RST <= '0'; D <= '1';
wait;
end process;

end behavioral;

-- simulated waveform

Explanation