Question

A T flip-flop is a 1-bit synchronous storage component alternative to the D flip-flop, with a slightly different interface. The T flip-flop has one input t to synchronously control the state of the flip-flop, as follows:

When t is 0, the flip-flop does not change its state value.

When t is 1, the flip-flop inverts its current state value (0 becomes 1, and 1 becomes 0).

Write a Verilog module for the T flip-flop using a behavioral model. The flip-flop should be triggered by the rising edge of the clock input. It should also have an asynchronous active-low reset input to reset the flip-flop state to zero

Answer 1

////VERILOG HDL FOR THE T-flipflop with asynchronous reset active high input//////////////

module T_ff(T,RST,CLK,Q,Q_bar);
input RST,T,CLK;
output Q,Q_bar;

reg Q,Q_bar;   //consider two variable signals
initial        //assign a reset state to the flipflop initially(its not                    mandatory)
    begin
      Q<=1'b0;
      Q_bar<=1'b1;
    end
always@(posedge CLK or posedge RST)//responds when clock raising edge or RESET raising edge is occurred.
begin
    if(RST==1'b1) begin //Check wheather reset is pressed or not
         Q<=1'b0;
         Q_bar<=1'b1;
       end
      else begin
        if(T==1'b0) begin //if T=0 Then assign previous state to the flipflop out put
         Q<=Q;
         Q_bar=Q_bar;
        end
     else begin   //if T=1 then Togle the state it have prevously
        Q<=~Q;
        Q<=~Q_bar;
      end
     end
   end
endmodule

(if you have any query leave a comment. Thank you)