Question

VHDL Code: Design a 16-bit 4-to-1 multiplexer using data-flow implementation style. Data inputs and output should be 16-bit vectors. In your test bench, you should include enough number of test cases to show the correctness of your design.

Answer 1

--VHDL code

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

entity mux4_1 is

Port ( I0 : in STD_LOGIC_VECTOR (15 downto 0); --Input1

I1 : in STD_LOGIC_VECTOR (15 downto 0); --Input2

I2 : in STD_LOGIC_VECTOR (15 downto 0); --Input3

I3 : in STD_LOGIC_VECTOR (15 downto 0); --Input4

Sel : in STD_LOGIC_VECTOR (1 downto 0); --Select input

mux_out : out STD_LOGIC_VECTOR (15 downto 0)); -- Multiplexer output

end mux4_1;

architecture Behavioral of mux4_1 is

begin

with Sel select

mux_out <= I0 when "00" , I1 when "01" , I2 when "10", I3 when "11";

end Behavioral;

-- Test Bench

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY tb_mux IS

END tb_mux;

ARCHITECTURE behavior OF tb_mux IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT mux4_1

PORT(

I0 : IN std_logic_vector(15 downto 0);

I1 : IN std_logic_vector(15 downto 0);

I2 : IN std_logic_vector(15 downto 0);

I3 : IN std_logic_vector(15 downto 0);

Sel : IN std_logic_vector(1 downto 0);

mux_out : OUT std_logic_vector(15 downto 0)

);

END COMPONENT;

  

--Inputs

signal I0 : std_logic_vector(15 downto 0) := (others => '0');

signal I1 : std_logic_vector(15 downto 0) := (others => '0');

signal I2 : std_logic_vector(15 downto 0) := (others => '0');

signal I3 : std_logic_vector(15 downto 0) := (others => '0');

signal Sel : std_logic_vector(1 downto 0) := (others => '0');

--Outputs

signal mux_out : std_logic_vector(15 downto 0);

-- No clocks detected in port list. Replace <clock> below with

-- appropriate port name

  

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: mux4_1 PORT MAP (

I0 => I0,

I1 => I1,

I2 => I2,

I3 => I3,

Sel => Sel,

mux_out => mux_out

);

-- Stimulus process

stim_proc: process

begin

  

wait for 100 ns;

I0 <= x"AAAA"; I1 <= x"BBBB"; I2 <= x"CCCC"; I3 <= x"DDDD";

Sel <= "00";

wait for 100 ns;

I0 <= x"EEEE";

wait for 100 ns;

Sel <= "01";

wait for 100 ns;

I1 <= x"EEEE";

wait for 100 ns;

Sel <= "10";

wait for 100 ns;

I2 <= x"EEEE";

wait for 100 ns;

Sel <= "11";

wait for 100 ns;

I3 <= x"EEEE";

wait;

end process;

END;

--Simulation on Xilinx ISim