On logisim or any circuit building program, design a counter that counts 9,8,7,6,5,4,3,2,1,0 then back to...

On logisim or any circuit building program, design a counter that counts 9,8,7,6,5,4,3,2,1,0 then back to 9. After, add to it's output a 7 segment decoder and it's display.

thank you!

Expert Solution

PRESENT STATE				NEXT STATE
Q3	Q2	Q1	Q0	Q3+	Q2+	Q1+	Q0+
0	0	0	0	1	0	0	1
0	0	0	1	0	0	0	0
0	0	1	0	0	0	0	1
0	0	1	1	0	0	1	0
0	1	0	0	0	0	1	1
0	1	0	1	0	1	0	0
0	1	1	0	0	1	0	1
0	1	1	1	0	1	1	0
1	0	0	0	0	1	1	1
1	0	0	1	1	0	0	0
1	0	1	0	X	X	X	X
1	0	1	1	X	X	X	X
1	1	0	0	X	X	X	X
1	1	0	1	X	X	X	X
1	1	1	0	X	X	X	X
1	1	1	1	X	X	X	X

We will be using D-Flip Flop for the Implementation as D - Input is same as next state expressions derived below using K-Maps.

Circuit is implemented and verified on MultiSim

Manojponduru answered 2 years ago

Question 3: A)Design a BCD counter. -The circuit counts from 0 to 9, then resets back...

Question 3: A)Design a BCD counter. -The circuit counts from 0 to 9, then resets back to 0 to restart the counting sequence. -The circuit has one input run/stop. If the input is 1, the eounter will count. If the input is 0, the counter will freeze in its current location until the input is set to 1 again. -The circuit has one output. It becomes 1 when the counter completes a cycle and starts the next one. Otherwise, that...

Construct a BCD counter that counts from 3 to 8, and back to 3.

Design a circuit using PIC 18F458, which counts the number of input pluses read by any...

Design a circuit using PIC 18F458, which counts the number of input pluses read by any input I/O port of the PIC 18 and show the pulses counting state on the 7-segment display. Hint: For Input pulses function generator or 555 Astable oscillator can be used.

design a counter that counts 0,3,2,4,1,5,7 and repeats using T-ff

Design a mod 5 counter as a (a) synchronous circuit (b) asynchronous circuit

(a) Design an FSM (only state diagram and state table) for a 3-bit counter that counts...

(a) Design an FSM (only state diagram and state table) for a 3-bit counter that counts through odd numbers downwards. Assume the reset state to be the lowest value of the counter. Use an active low reset to reset the counter. (b) Write a behavioral VHDL code that implements the FSM. (c) Write a VHDL test bench to test the FSM.

Using Multisim, design a 2-bit, synchronous binary counter and verify that it counts in the right...

Using Multisim, design a 2-bit, synchronous binary counter and verify that it counts in the right sequence, Can count up or down and use any FF you desire; 4 screen shots in total: 1 for each input combination

1. Build a circuit in Logisim with the following characteristics: The circuit should have 3 inputs...

1. Build a circuit in Logisim with the following characteristics: The circuit should have 3 inputs - A, B, and C. The circuit should have 1 output - W. The output should be a 1 if the three inputs would form a binary number that is a multiple of 3. (Don't forget that 0 is a multiple of 3!) The circuit should only use AND gates, OR gates, NOT gates, input pins, output pins, and wires. (See if you can...

Design a counter using JK Flip Flops and Gates, that counts 3,1,4,2,9,2,2,4 using a Moore Machine....

Design a counter using JK Flip Flops and Gates, that counts 3,1,4,2,9,2,2,4 using a Moore Machine. Show Moore machine state diagram, state table and cirucit.

Objective: Design, construct, and test a three-bit counter that counts up or down. An enable input...

Objective: Design, construct, and test a three-bit counter that counts up or down. An enable input E determines whether the counter is on or off.  If E=0, the counter is disabled and remains at its present count even though clock pulses are applied to the flip-flops.  If E=1, the counter is enabled and a second input, x, determines the direction of the count.  If x=1, the circuit counts upward with the sequence 000, 001, 010, 011, 100,...

Question