Design a counter using JK Flip Flops and Gates, that counts
3,1,4,2,9,2,2,4 using a Moore Machine. Show Moore machine state
diagram, state table and cirucit.
Using Multisim, design a 2-bit, synchronous binary counter and
verify that it counts in the right sequence, Can count up or down
and use any FF you desire; 4 screen shots in total: 1 for each
input combination
On logisim or any circuit building program, design a
counter that counts 9,8,7,6,5,4,3,2,1,0 then back to 9. After, add
to it's output a 7 segment decoder and it's display.
thank you!
(a) Design an FSM (only state diagram and state table) for a
3-bit counter that counts through odd numbers downwards. Assume the
reset state to be the lowest value of the counter. Use an active
low reset to reset the counter.
(b) Write a behavioral VHDL code that implements the FSM.
(c) Write a VHDL test bench to test the FSM.
Design a Count-up Counter in Aiken code with following flip
flops: a) D-FF (Active edge is high to low) b) SR-FF (Active edge
is high to low) c) Use of output of circuit in part (b) and minimum
number of logic gates for getting the Countdown counter in Aiken
code