Question

(a) Design an FSM (only state diagram and state table) for a 3-bit counter that counts through odd numbers downwards. Assume the reset state to be the lowest value of the counter. Use an active low reset to reset the counter.

(b) Write a behavioral VHDL code that implements the FSM.

(c) Write a VHDL test bench to test the FSM.

Answer 1

Part A)

Part B)

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity count_down is
port (
clk : in std_logic;
rst : in std_logic;
out1 : out std_logic_vector(2 downto 0)
);
end count_down;

architecture behavioural of count_down is
type state_type is (A, B, C, D);
signal cur_state, next_state : state_type;
begin

Process1 : process(clk) --current state logic
begin
if (clk'event and clk = '1') then
if (rst = '1') then
cur_state <= A;
else
cur_state <= next_state;
end if;
end if;
end process Process1;

Process2 : process(cur_state, X) --next state and output logic
begin
case (cur_state) is
when A => out1 <= "001";
next_state <= D;
when B => out1 <= "011";
next_state <= A;
when C => out1 <= "101";
next_state <= B;
when others => out1 <= "111";
next_state <= C;
  
end case;
end process Process2;

end behavioural;

Part C)
--Testbench of Count Down FSM
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity tb_counters is
end tb_counters;

architecture Testbench of tb_counters is

component count_down
Port ( clk : in std_logic; -- clock input
rst : in std_logic; -- reset input
out1 : out std_logic_vector(2 downto 0) -- output 3-bit counter
);
end component;

signal rst, clk : std_logic;
signal out1 : std_logic_vector(2 downto 0);

begin
dut: DOWN_COUNTER port map (clk => clk, rst => rst, out1 => out1);

-- Clock process definitions
clock_process :process
begin
clk <= '0';
wait for 10 ns;
clk <= '1';
wait for 10 ns;
end process;

-- Stimulus process
stim_proc: process
begin   
-- hold reset state for 100 ns.
reset <= '0';
wait for 20 ns;   
reset <= '1';
wait for 400 ns;   
wait;
end process;

end Testbench;