Question

1) A. In a 1 bit half adder which design is the sizing of the transistor most area efficient, CMOS logic, transmission gate, or dynamic logic. Explain.

B. If the W/L of the transistors at gate level are the same, which one will be the fastest driving the same amount of load. Explain.

C. Which is the most power efficient?

Answer 1

Question 1.

Answer: A) CMOS logic

First of all, let us consider the sizing of an inverter. We have already seen that the propagation delay of the gate is proportional to (R_p + R_n)C_L. The delay of an inverter can be minimized by keeping the output capacitance small or by decreasing the on resistance of the transistor. The C_L consists of the diffusion capacitance of the transistors, the interconnect capacitance and the fan-out capacitance. Careful layout helps to reduce the diffusion and interconnect capacitances. The on-resistance of the transistor is inversely proportional to the W/L ratio of the device. It is known that the mobility of holes are approximately 2.5 times lower than that of electrons in Silicon. Thus, a 2.5 time wider PMOS transistor is needed to match its on-resistance to that of pull-down NMOS device. With such a sizing of NMOS and PMOS width, we can design an inverter with a symmetrical VTC (Voltage Transfer Characteristics) and equal high-to-low and low-to-high propagation delays. The diffusion capacitance is also increased with increasing widths and careful optimization is required.

B. The W/L ratio is linked to the trans-conductance and the current capability, together with the multiplicity factor m. A higher w/l ratio increases the current gain and subsequently a higher current for a given Vg. The same is for a higher m that means m·W/L.In practice, for the gain stages are useful large transistors, i.e. large W/L ratios or/and large m. As example, the differential input stage of OpAmps needs high gain. However, the good matching of the input differential stage has to be considered as well. In the current mirrors, a higher transistor gate length is beneficial, for a better matching of the mirror’s currents. You can play with these parameters in simulations to observe the impact of the length on the mirrors current matching.In general, a larger transistor ensures a better matching because it minimizes the edge effects, but this is paid with a significant area price.

C. CMOS logic is most power efficient.